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datasheet apr 2010 1 order number: 208033-02 numonyx ? axcell? p30-65nm flash memory 128-mbit, 64-mbit single bit per cell (sbc) datasheet product features ? high performance: ? 65ns initial access time for easy bga and quad+ ? 75ns initial access time for tsop ? 25ns 8-word asynchronous-page read mode ? 52mhz with zero wait states, 17ns clock-to- data output synchronous-burst read mode ? 4-, 8-, 16- and continuous-word options for burst mode ? 1.8v low power buffered programming at 1.8 mbyte/s (typ) using 256-word buffer ? buffered enhanced factory programming at 3.2mbyte/s (typ) using 256-word buffer ? architecture: ? asymmetrically-blocked architecture ? four 32-kbyte parameter blocks: top or bottom configuration ? 128-kbyte array blocks ? blank check to verify an erased block ? voltage and power: ? vcc (core) voltage: 1.7v ? 2.0v ? vccq (i/o) voltage: 1.7v ? 3.6v ? standby current: 30a(typ)/55a(max) ? continuous synchronous read current: 23ma (typ)/28ma (max) at 52mhz ? enhanced security: ? absolute write protection: vpp = vss ? power-transition erase/program lockout ? individual zero-latency block locking ? individual block lock-down capability ? password access feature ? one-time programmable register: ? 64 otp bits, programmed with unique information by numonyx ? 2112 otp bits, available for customer programming ? software: ? 20 s (typ) program suspend ? 20 s (typ) erase suspend ? basic command set and extended function interface (efi) command set compatible ? common flash interface capable ? density and packaging: ? 56-lead tsop (128-mbit, 64-mbit) ? 64-ball easy bga (128-mbit, 64-mbit) ? 88-ball quad+ package (128-mbit) ? 16-bit wide data bus ? quality and reliability: ? jesd47e compliant ? operating temperature: ?40c to +85c ? minimum 100,000 erase cycles ? 65nm process technology
datasheet apr 2010 2 order number: 208033-02 legal lines and disclaimers information in this document is provided in connection with numo nyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical co ntrol or safety systems, or in nuclear f acility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no respon sibility whatsoever for conf licts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to ob tain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx, the numonyx logo, and axcell are trademarks or registered trademarks of numonyx , b.v. or its subsidiaries in other co untries. *other names and brands may be claimed as the property of others. copyright ? 2010, numonyx, b.v., all rights reserved.
datasheet apr 2010 3 order number: 208033-02 p30-65nm sbc contents 1.0 functional description ............................................................................................... 5 1.1 introduction ....................................................................................................... 5 1.2 overview ........................................................................................................... 5 1.3 memory map....................................................................................................... 6 2.0 package information ................................................................................................. 7 2.1 56-lead tsop..................................................................................................... 7 2.2 64-ball easy bga package .................................................................................... 8 2.3 quad+ scsp packages ...................................................................................... 10 3.0 pinouts/ballouts ..................................................................................................... 11 4.0 signals .................................................................................................................... 14 5.0 bus operations ........................................................................................................ 16 5.1 read - asynchronous mode................................................................................. 16 5.2 read - synchronous mode .................................................................................. 16 5.3 write ............................................................................................................... 17 5.4 output disable .................................................................................................. 17 5.5 standby ........................................................................................................... 17 5.6 reset............................................................................................................... 18 6.0 command set .......................................................................................................... 19 6.1 device command codes ..................................................................................... 19 6.2 device command bus cycles .............................................................................. 20 7.0 read operation ........................................................................................................ 22 7.1 read array ....................................................................................................... 22 7.2 read device identifier........................................................................................ 22 7.3 read cfi .......................................................................................................... 23 7.4 read status register ......................................................................................... 23 7.5 clear status register ......................................................................................... 23 8.0 program operation .................................................................................................. 24 8.1 word programming ........................................................................................... 24 8.2 buffered programming ....................................................................................... 24 8.3 buffered enhanced factory programming............ .................................................. 25 8.4 program suspend .............................................................................................. 27 8.5 program resume............................................................................................... 28 8.6 program protection............................................................................................ 28 9.0 erase operation ....................................................................................................... 29 9.1 block erase ...................................................................................................... 29 9.2 blank check ..................................................................................................... 29 9.3 erase suspend .................................................................................................. 30 9.4 erase resume................................................................................................... 30 9.5 erase protection ................................................................................................ 30 10.0 security ................................................................................................................... 31 10.1 block locking.................................................................................................... 31 10.2 selectable otp blocks ........................................................................................ 33 10.3 password access ............................................................................................... 33 11.0 register ................................................................................................................... 34 11.1 status register (sr) .......................................................................................... 34 11.2 read configuration register (rcr) .................. .................................................... 34
p30-65nm sbc datasheet apr 2010 4 order number: 208033-02 11.3 one-time programmable (otp) registers .............................................................40 12.0 power and reset specifications ...............................................................................43 12.1 power-up and power-down .................................................................................43 12.2 reset specifications ...........................................................................................43 12.3 power supply decoupling....................................................................................44 13.0 maximum ratings an d operating conditions ............................................................45 13.1 absolute maximum ratings .................................................................................45 13.2 operating conditions..........................................................................................45 14.0 electrical specifications ...........................................................................................46 14.1 dc current characteristics ......................... .........................................................46 14.2 dc voltage characteristics ..................................................................................47 15.0 ac characteristics ....................................................................................................48 15.1 ac test conditions.............................................................................................48 15.2 capacitance ......................................................................................................49 15.3 ac read specifications ......................................................................................50 15.4 ac write specifications .......................................................................................54 15.5 program and erase characteristics ................. ......................................................58 16.0 ordering information ...............................................................................................59 a supplemental reference information .......................................................................61 a.1 common flash interface .....................................................................................61 a.2 flowcharts ........................................................................................................73 a.3 write state machine ...........................................................................................83 b conventions - additional documentation .................................................................87 b.1 acronyms .........................................................................................................87 b.2 definitions and terms ........................................................................................87 c revision history .......................................................................................................89
datasheet apr 2010 5 order number:208033-02 p30-65nm sbc 1.0 functional description 1.1 introduction this document provides information about the numonyx ? axcell tm p30-65nm single bit per cell (sbc) flash memory and describes it s features, operations, and specifications. p30-65nm sbc device is offered in 64-mbit and 128-mbit. benefits include high-speed interface nor device, and support for code and data storage. features include high- performance synchronous-burst read mode, a dramatical improvement in buffer program time through larger buffer size, fa st asynchronous access times, low power, flexible security options, and three industry-standard package choices. p30-65nm sbc device is manufactured using 65nm process technology. 1.2 overview p30-65nm sbc device provides high performance on a 16-bit data bus. individually erasable memory blocks are sized for optimum code and data storage. upon initial power-up or return from reset, the device defaults to asynchronous page-mode read. configuring the read configuration register (rcr) enables synchronous burst-mode reads. in synchronous burst mode, output data is synchronized with a user-supplied clock signal. a wait signal provides ea sy cpu-to-flash memory synchronization. in addition to the enhanced architecture and interface, the device incorporates technology that enables fast buffer progra m and erase operations. the device features a 256-word buffer to enable optimum prog ramming performance, which can improve system programming throughput time significantly to 1.8 mbyte/s. designed for low-voltage systems, the p30-65nm sbc device supports read operations with vcc at 1.8v, and erase and program operations with vpp at 1.8v or 9.0v. buffered enhanced factory programming provides the fastest flash array programming performance with vpp at 9.0v, which increa ses factory throughput with 3.2mbyte/s. with vpp at 1.8v, vcc and vpp can be tied together for a simple, ultra low power design. in addition to voltage flexibility, a dedicated vpp connection provides complete data protection when vpp v pplk . the command user interface is the interf ace between the system processor and all internal operations of the device. an in ternal write state machine automatically executes the algorithms and timings necessary for block erase and program. a status register indicates erase or program completion and any errors that may have occurred. a device command sequence invokes program and erase automation. each erase operation erases one block. the erase suspend feature allows system software to pause an erase cycle to read or program data in another block. program suspend allows system software to pause programming to read other locations. the otp register allows unique flash device identification that can be used to increase system security. the individual block lock feature provides zero-latency block locking and unlocking. the p30-65nm sbc device adds enhanced protection via password access; this new feature allows write and/or read access protection of user-defined blocks. in addition, the p30-65nm sbc devi ce also has backward-compatible one-time programmable (otp) permanent block locking security feature.
p30-65nm sbc datasheet apr 2010 6 order number: 208033-02 1.3 memory map note: a1 is the least significant address bit for tsop and easy bga while a0 for the quad+ package. unless otherwise indicated, for th e purpose of brevity, this document will consolidate all discussions to a1 as the least significant address bit. figure 1: p30-65nm sbc memory map (64-mbit and 128-mbit densities) 16- kword block 64- kword block 16- kword block bottom boot word wide (x16) mode 7f0000 7fffff 000000 ? 003fff 64- kword block 3f0000 3fffff 1 0 130 128-mbit a<23: 1> 128- mbit 16- kword block 16- kword block 64- kword block 64- kword block 004000 ? 007fff 008000 ? 00bfff 00c000? 00ffff 010000 ? 01ffff 020000 ? 02ffff 2 3 4 5 66 16- kword block 16- kword block top boot word wide (x 16) mode 64- kword block 128 127 16- kword block 16- kword block 64- kword block 64- kword block 129 130 0 1 126 000000 ?00ffff 010000 ?01ffff 7f 0000 ? 7f4000 ?7f7000 7f8000 ? 7fbfff 7f c 0 00 ? 7fffff 7e0000 ? 7effff 64-mbit ? ? a<22:1> 64-mbit 128-mbit a<23: 1 > 128- mbit 16- kword block 16- kword block top boot word wide (x16) mode 64- kword block 64 63 16- kword block 16- kword block 64- kword block 64- kword block 65 66 0 1 62 000000 ?00ffff 010000 ?01ffff 3f0000 ? 3f3fff 3f4000 ? 3f7fff 3f8000 ? 3fbfff 3fc000 ? 3fffff 3e0000 ? 3effff a<22:1> 64-mbit 64-mbit 7f3fff
datasheet apr 2010 7 order number:208033-02 p30-65nm sbc 2.0 package information 2.1 56-lead tsop figure 2: tsop mechanical specifications table 1: tsop package dimensions (sheet 1 of 2) product information symbol millimeters inches min nom max min nom max package height a - - 1.200 - - 0.047 standoff a 1 0.050 - - 0.002 - - package body thickness a 2 0.965 0.995 1.025 0.038 0.039 0.040 lead width b 0.100 0.150 0.200 0.004 0.006 0.008 lead thickness c 0.100 0.150 0.200 0.004 0.006 0.008 package body length d 1 18.200 18.400 18.600 0.717 0.724 0.732 package body width e 13. 800 14.000 14.200 0.543 0.551 0.559 lead pitch e - 0.500 - - 0.0197 - terminal dimension d 19.800 20.00 20.200 0.780 0.787 0.795 lead tip length l 0.500 0.600 0.700 0.020 0.024 0.028 a 0 l detail a y d c z pin 1 e d 1 b detail b see detail a e see detail b a 1 seating plane a 2 see note 2 see notes 1 and 3
p30-65nm sbc datasheet apr 2010 8 order number: 208033-02 2.2 64-ball easy bga package lead count n - 56 - - 56 - lead tip angle 0 3 5 0 3 5 seating plane coplanarity y - - 0.100 - - 0.004 lead to package offset z 0 .150 0.250 0.350 0.006 0.010 0.014 notes: 1. one dimple on package denotes pin 1. 2. if two dimples, then the larger dimple denotes pin 1. 3. pin 1 will always be in the upper left corner of the package, in reference to the product mark. figure 3: easy bga mechanical specifications (10x13x1.2 mm) table 1: tsop package dimensions (sheet 2 of 2) product information symbol millimeters inches min nom max min nom max e seating plane s1 s2 e top view - ball side down bottom view - ball side up y a a1 d ball a1 corner a2 note: drawing not to scale a b c d e f g h 87 6 543 2 1 8 7 6 5 4 3 2 1 a b c d e f g h b ball a1 corner table 2: easy bga package dimensions for 10x13x1.2 mm (sheet 1 of 2) product information symbol millimeters inches min nom max min nom max package height a - - 1.200 - - 0.0472 ball height a1 0.250 - - 0.0098 - - package body thickness a2 - 0.780 - - 0.0307 - ball (lead) width b 0.310 0.410 0.510 0.0120 0.0160 0.0200 package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976
datasheet apr 2010 9 order number:208033-02 p30-65nm sbc package body length e 12.900 13.000 13.100 0.5079 0.5118 0.5157 pitch e - 1.000 - - 0.0394 - ball (lead) count n - 64 - - 64 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 distance along d s1 1.400 1.500 1.600 0.0551 0.0591 0.0630 corner to ball a1 distance along e s2 2.900 3.000 3.100 0.1142 0.1181 0.1220 note: daisy chain evaluation unit information is at nu monyx? flash memory packaging technology http:// developer.numonyx.com/design/flash/packtech. table 2: easy bga package dimensions for 10x13x1.2 mm (sheet 2 of 2) product information symbol millimeters inches min nom max min nom max
p30-65nm sbc datasheet apr 2010 10 order number: 208033-02 2.3 quad+ scsp packages figure 4: 128-mbit, 88-ball (80 active) quad+ scsp specifications (8x10x1.2 mm) millimeters inches dimensions symbol min nom max min nom max package height a - - 1.200 - - 0.0472 ball height a 1 0.200 - - 0.0079 - - package body thickness a 2 - 0.860 - - 0.0339 - ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body width d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body length e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e - 0.800 - - 0.0315 - ball (lead) count n - 88 - - 88 - seating plane coplanarity y - - 0.100 - - 0.0039 corner to ball a1 dis tance a long e s 1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d s 2 0.500 0.600 0.700 0.0197 0.0236 0.0276 top view - ball down bottom view - ball up a a 2 d e y a 1 drawing not to scale. s 2 s 1 a c b e d g f j h k l m e 1 2 3 4 5 6 7 8 b a c b e d g f j h k l m 12345678 a1 index mark
datasheet apr 2010 11 order number:208033-02 p30-65nm sbc 3.0 pinouts/ballouts notes: 1. a1 is the least sign ificant address bit. 2. a23 is valid for 128-mbit densities; otherwise, it is a no connect (nc). 3. a22 is valid for 64-mbit de nsities and above; otherwise, it is a no connect (nc). 4. no internal connection on pin 13; it may be driven or floa ted. for legacy 130nm designs, this pin can be tied to vcc. 5. one dimple on package denotes pin 1 whic h will always be in the upper left corner of the package, in reference to the product mark. figure 5: 56-lead tsop pinout (6 4-mbit and 128-mbit densities) 56-lead tsop pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a14 a13 a12 a10 a9 a11 a23 a21 vss a22 nc wp# a20 we# a19 a8 a7 a18 a6 a4 a3 a5 a2 rfu vss rfu wait dq15 dq7 a17 dq14 dq13 dq5 dq6 dq12 adv# clk dq4 rst# a16 dq3 vpp dq10 vccq dq9 dq2 dq1 dq0 vcc dq8 oe # ce# a1 vss a15 dq11
p30-65nm sbc datasheet apr 2010 12 order number: 208033-02 notes: 1. a1 is the least significant address bit. 2. a23 is valid for 128-mbit densities; otherwise, it is a no connect. 3. a22 is valid for 64-mbit densities and ab ove; otherwise, it is a no connect (nc). 4. one dimple on package denotes pin 1 which will always be in the upper left corner of the package, in reference to the product mark. figure 6: 64-ball easy bga ballout (64-mbit and 128- mbit densities) 1 8 234 5 67 easy bga top view- ball side down easy bga bottom view- ball side up 1 8 2 3 4 5 6 7 h g f e d c b a h g f e d c a a2 vss a9 a14 ce# a19 rfu rfu rfu vss vcc dq13 vss dq7 rfu vss a3 a7 a10 a15 a12 a20 a21 wp# a4 a5 a11 vccq rst# a16 a17 vccq rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe# dq0 dq10 dq12 dq11 wait adv# we# a23 rfu dq2 dq5 vccq dq14 dq6 a1 a6 a8 a13 vpp a18 a22 vcc a23 a4 a5 a11 vccq rst# a16 a17 vccq a1 a6 a8 a13 vpp a18 a22 vcc a3 a7 a10 a15 a12 a20 a21 wp# rfu dq8 dq1 dq9 dq4 dq3 dq15 clk rfu oe # dq0 dq10 dq12 dq11 wait adv# we# rfu dq2 dq5 vccq dq14 dq6 a2 vss a9 a14 ce# a19 rfu rfu rfu vss vcc dq13 vss dq7 rfu vss b
datasheet apr 2010 13 order number:208033-02 p30-65nm sbc notes: 1. a22 is valid for 128-mbit densities; otherwise, it is a no connect (nc). 2. a21 is valid for 64-mbit de nsities and above; otherwise, it is a no connect (nc). 3. f2-ce# and f2-oe# are no connect (nc) for all densities. 4. unlike tsop and easy bga, a0 is the le ast significant address bit for the quad+ package. unless otherwise indicated, for the purpose of brevity, this document w ill consolidate all later discussions to a1 as the least significant address bit. figure 7: quad+ scsp ballout and signals (128-mbit) pin 1 12345678 a du du depop depop depop depop du du a b a4 a18 a19 vss vcc vcc a21 a11 b c a5 rfu rfu vss rfu clk a22 a12 c d a3 a17 vpp rfu rfu a9 a13 d e a2 a7 wp# adv# a20 a10 a15 e f a1 a6 rfu rst# we# a8 a14 a16 f g a0 dq8 dq2 dq10 dq5 dq13 wait f2-ce# g h rfu dq0 dq1 dq3 dq12 dq14 dq7 f2-oe# h j rfu f1-oe# dq9 dq11 dq4 dq6 dq15 vccq j k f1-ce# rfu rfu rfu rfu vcc vccq rfu k l vss vss vccq vcc vss vss vss vss l m du du depop depop depop depop du du m 12345678 control signals reserved for future use data do not use power/ground address top view - ball side down legends: de-populated ball rfu rfu
p30-65nm sbc datasheet apr 2010 14 order number: 208033-02 4.0 signals table 3: tsop and easy bga signal descriptions symbol type name and function a[max:1] input address inputs: device address inputs. 128-mbit: a[23:1], 64-mbit: a[22:1]. dq[15:0] input/ output data input/outputs: inputs data and commands during write cycles; outputs data during reads of memory, status register, otp register, and read configuration register. data balls float when the ce# or oe# are deasserted. data is internally latched during writes. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid cl k edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. warning: designs not using adv# must tie it to vss to allow addresses to flow through. ce# input chip enable: active low input. ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers, de coders, and sense amplifiers are active. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. warning: chip enable must be high when device is not in use. clk input clock: synchronizes the device with the system?s bus frequency in synchronous-read mode. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. warning: designs not using clk for synchronous read mode must tie it to vccq or vss. oe# input output enable: active low input. oe# low enables the device?s output data buffers during read cycles. oe# high places the data outputs and wait in high-z. rst# input reset: active low input. rst# resets internal au tomation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal operation. exit from reset places the device in asynchronous read array mode. wait output wait: indicates data valid in synchronous array or non-array burst reads. rcr.10, (wt) determines its polarity when asserted. wait?s active output is v ol or v oh when ce# and oe# are v il . wait is high-z if ce# or oe# is v ih . ? in synchronous array or non-array read modes, wait indicates in valid data when asserted and valid data when deasserted. ? in asynchronous page mode, and all write modes, wait is deasserted. we# input write enable: active low input. we # controls writes to the device. address and data are latched on the rising edge of we#. wp# input write protect: active low input. wp# low enables the lock-down mechanism. blocks in lock- down cannot be unlocked with the unlock command. wp# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. vpp power/ input erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when vpp v pplk . block erase and program at invalid vpp voltages should not be attempted. set vpp = v ppl for in-system program and erase operations . to accommodate resistor or diode drops from the system supply, the v ih level of vpp can be as low as v ppl min. vpp must remain above v ppl min to perform in-system flash modification. vpp may be 0 v during read operations. v pph can be applied to array blocks for 1000 cycles maximum and to parameter blocks for 2500. vpp can be connected to 9 v for a cumulative total not to exceed 80 hours. extended use of this pin at 9 v may reduce block cycling capability. vcc power device core power supply: core (logic) source voltage. writes to the flash array are inhibited when vcc v lko . operations at invalid vcc voltages should not be attempted. vccq power output power supply: output-driver source voltage. vss power ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserved by numonyx for future device functionality and enhancement. these should be treated in the same way as a don?t use (du) signal. du ? don?t use: do not connect to any other signal, or power supply; must be left floating. nc ? no connect: no internal connection; can be driven or floated.
datasheet apr 2010 15 order number:208033-02 p30-65nm sbc table 4: quad+ scsp signal descriptions symbol type name and function a[max:0] input address inputs: device address inputs. 128-mbit: a[22:0]. note: unlike tsop and easy bga, a0 is the least significant addr ess bit for the quad+ package. unless otherwise indicated, for the purpose of brevit y, this document will co nsolidate all discussions to a1 as the least si gnificant address bit. dq[15:0] input/ output data input/outputs: inputs data and commands during write cycles; outputs data during memory, status register, protection register, and read configuration register reads. data balls float when the ce# or oe# are deasserted. data is internally latched during writes. adv# input address valid: active low input. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid cl k edge with adv# low, whichever occurs first. in asynchronous mode, the address is latched when adv# going high or continuously flows through if adv# is held low. warning: designs not using adv# must tie it to vss to allow addresses to flow through. f1-ce# input flash chip enable: active low input. f1-ce# low selects the associated flash memory die. when asserted, flash internal control logic, input buffers , decoders, and sense amplifiers are active. when deasserted, the associated flash die is deselected , power is reduced to standby levels, data and wait outputs are placed in high-z state. warning: chip enable must be driven high when device is not in use. clk input clock: synchronizes the device with the system?s bus frequency in synchronous-read mode. during synchronous read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge with adv# low, whichever occurs first. warning: designs not using clk for synchronous read mode must tie it to vccq or vss. f1-oe# input output enable: active low input. f1-oe# low enables th e device?s output data buffers during read cycles. f1-oe# high places th e data outputs and wait in high-z. rst# input reset: active low input. rst# resets internal au tomation and inhibits write operations. this provides data protection during power transitions. rst# high enables normal operation. exit from reset places the device in asynchronous read array mode. wait output wait: indicates data valid in synchronous array or non-array burst reads. read configuration register bit 10 (rcr.10, wt) determines its polari ty when asserted. wait?s active output is v ol or v oh when f1-ce# and f1-oe# are v il . wait is high-z if f1-ce# or f1-oe# is v ih . ? in synchronous array or non-array read modes, wait indicates invalid data when asserted and valid data when deasserted. ? in asynchronous page mode, and all write modes, wait is deasserted. we# input write enable: active low input. we# controls writes to the device. address and data are latched on the rising edge of we#. wp# input write protect: active low input. wp# low enables the lock-down mech anism. blocks in lock- down cannot be unlocked with the unlock command. wp# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. vpp power/ lnput erase and program power: a valid voltage on this pin allows erasing or programming. memory contents cannot be altered when v pp v pplk . block erase and program at invalid v pp voltages should not be attempted. set v pp = v ppl for in-system program and erase operations. to accommodate resistor or diode drops from the system supply, the v ih level of v pp can be as low as v ppl min. v pp must remain above v ppl min to perform in-system flash modification. vpp may be 0 v during read operations. v pph can be applied to main blocks for 1000 cycl es maximum and to parameter blocks for 2500 cycles. vpp can be connected to 9 v for a cumulative total not to exceed 80 hours. extended use of this pin at 9 v may reduce block cycling capability. vcc power device core power supply: core (logic) source voltage. writ es to the flash array are inhibited when v cc v lko . operations at invalid v cc voltages should not be attempted. vccq power output power supply: output-driver source voltage. vss power ground: connect to system ground. do not float any vss connection. rfu ? reserved for future use: reserved by numonyx for future device functionality and enhancement. these should be treated in the same way as a do not use (du) signal. du ? do not use: do not connect to any other signal, or power supply; must be left floating. nc ? no connect: no internal connection; can be driven or floated.
p30-65nm sbc datasheet apr 2010 16 order number: 208033-02 5.0 bus operations ce# low and rst# high enable device read operations. the device internally decodes upper address inputs to determine the acce ssed block. adv# low opens the internal address latches. oe# low activates the outp uts and gates selected data onto the i/o bus. bus cycles to/from the p30-65nm sbc device conform to standard microprocessor bus operations. table 5, ?bus operations summary? summarizes the bus operations and the logic levels that must be applied to the device control signal inputs. 5.1 read - asynchronous mode to perform an asynchronous page or single word read, an address is driven onto the address bus, and ce# is assert ed. adv# can be driven high to latch the address, or it must be held low throughout the read cycl e. we# and rst# must already have been deasserted. wait is set to a deasserted state during asynchronous page mode and single word mode as determined by rcr.10 . clk is not used for asynchronous page- mode reads, and is ignored. after oe# is asserted, the data is driven onto dq[15:0] after an initial access time t avqv or t glqv delay. (see table 25, ?ac read specifications? on page 50 ). note: if only asynchronous reads are to be performed, clk should be tied to a valid v ih level, wait signal can be floated and adv# must be tied to ground. in asynchronous page mode, eight data words are ?sensed? simultaneously from the flash memory array and loaded into an internal page buffer. the buffer word corresponding to the initial address on the address bus is driven onto dq[15:0] after the initial access delay. the lowest three address bits determine which word of the 8-word page is output from the data buffer at any given time. refer to the following waveforms for more detailed information: figure 19, ?asynchronous single-word read (adv# low)? on page 51 , and figure 20, ?asynchronous single-word read (adv# latch)? on page 52 , and figure 21, ?asynchronous page-mode read timing? on page 52 . 5.2 read - synchronous mode to perform a synchronous burst read on array or non-array, an initial address is driven onto the address bus, and ce# is asserted . we# and rst# must already have been deasserted. adv# is asserted, and then deasserted to latch the address. alternately, table 5: bus operations summary bus operation rst# clk adv# ce# oe# we# wait dq[15:0] notes read asynchronous v ih xl l l h deasserted output 2 synchronous v ih running l l l h driven output - write v ih x l l h l high-z input 1,2 output disable v ih x x l h h high-z high-z 2 standby v ih x x h x x high-z high-z 2 reset v il x x x x x high-z high-z 2,3 notes: 1. refer to the table 7, ?command bus cycles? on page 21 for valid dq[15:0] during a write operation. 2. x = don?t care (h or l). 3. rst# must be at v ss 0.2v to meet the maximum specified power-down current.
datasheet apr 2010 17 order number:208033-02 p30-65nm sbc adv# can remain asserted throughout the burst access, in which case the address is latched on the next valid clk edge while ad v# is asserted. once oe# is asserted, the the first word is driven onto dq[15:0] on the next valid clk edge after initial access latency delay (see section 11.2.2, ?latency count (rcr[13:11])? on page 36 ). subsequent data is output on valid clk edges following a minimum delay t chqv (see table 25, ?ac read specifications? on page 50 ). however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. the wait signal indicates data valid when the device is operating in synchronous mode (rcr.15=0). the wait signal is only ?deassert ed? when data is valid on the bus. when the device is operating in synchronous non-array read mode, such as read status, read id, or read query, the wait signal is also ?deasserted? when data is valid on the bus. wait behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. refer to the following waveforms for more detailed information: figure 22, ?synchronous single-word array or non-array read timing? on page 53 , and figure 23, ?continuous burst read, showing an output delay timing? on page 53 , and figure 24, ?synchronous burst-mode four-word read timing? on page 54 . 5.3 write to perform a write operation, both ce# and we# are asserted while rst# and oe# are deasserted. during a write operation, address and data are latched on the rising edge of we# or ce#, whichever occurs first. table 7, ?command bus cycles? on page 21 shows the bus cycle sequence for each of the supported device commands, while table 6, ?command codes and definitions? on page 19 describes each command. see table 26, ?ac write specifications? on page 54 for signal-timing details. when the device is operating in write operat ions, wait is set to a deasserted state as determined by rcr.10. note: write operations with invalid vcc and/or vpp voltages can produce spurious results and should not be attempted. 5.4 output disable when oe# is deasserted, device outputs dq[15:0] are disabled and placed in a high - impedance (high-z) state, wait is also placed in high-z. 5.5 standby when ce# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. in standby, the data outputs are placed in high-z, independent of the level placed on oe#. standby current, i ccs , is the average current measured over any 5ms time interval, 5 s after ce# is deasserted. during standby, average current is measured over the same time interval 5 s after ce# is deasserted. when the device is deselected (while ce# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed.
p30-65nm sbc datasheet apr 2010 18 order number: 208033-02 5.6 reset as with any automated device, it is important to assert rst# when the system is reset. when the system comes out of reset, the sy stem processor attempts to read from the flash memory if it is the system boot device. if a cpu reset occurs with no flash memory reset, improper cpu initializatio n may occur because the flash memory may be providing status information rather th an array data. flash memory devices from numonyx tm allow proper cpu initialization followi ng a system reset through the use of the rst# input. after initial power-up or reset, the device defaults to asynchronous read array mode, and the status register is set to 0x80. when rst# is driven low (rst# asserted), the flash device enters reset mode. then all internal circuits are de-energized, and the ou tput drivers are placed in high-z. if rst# is asserted during a program or erase oper ation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid. a device reset also clears the status register. see table 18, ?power and reset? on page 43 for rst# timing detail. when rst# is driven high (rst# deasserted ), a minimum wait is required before the flash device is able to perform normal operations. please consider t phqv (r5) and t phwl (w1) during system design. see table 25, ?ac read specifications? on page 50 . and section 26, ?ac write specifications? on page 54 . after this wake - up interval passes, normal operation is ready for execution.
datasheet apr 2010 19 order number:208033-02 p30-65nm sbc 6.0 command set 6.1 device command codes the flash command user interface (cui) prov ides access to device read, write, and erase operations. the cui does not occupy an addressable memory location; it is part of the internal logic which allows the flash device to be controlled. the write state machine provides the management for its internal erase and program algorithms. commands are written to the cui to control flash device operations. ta b l e 6 , ?command codes and definitions? describes all valid command codes. for operations that involve multiple comm and cycles, the possibility exists that the subsequent command does not get issued in the proper sequence. when this happens, the cui sets status register bits sr[5,4] to indicate a command sequence error. table 6: command codes and de finitions (sheet 1 of 2) mode code device mode description read 0xff read array places the device in read arra y mode. array data is output on dq[15:0]. 0x70 read status register places the device in read status register mode. the device enters this mode after a program or erase command is issued. sr data is output on dq[7:0]. 0x90 read device id or read configuration register (rcr) places device in read device iden tifier mode. subsequent reads output manufacturer/device codes, configuration register data, block lock status, or otp register data on dq[15:0]. 0x98 read cfi places the device in read query mode. subsequent reads output common flash interface (cfi) information on dq[7:0]. 0x50 clear status register the wsm can only set sr error bits. the clear status register command is used to clear the sr error bits. write 0x40 word program setup first cycle of a 2-cycle programming command; prepares the cui for a write operation. on the next write cycle, the address and data are latched and the wsm executes the programming algorith m at the addressed location. during program operations, the device responds only to read status register and program suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the sr data for synchronous non-array reads. the read array command must be issued to read array data after programming has finished. 0xe8 buffered program this command loads a variable number of words up to the buffer size of 256 words onto the program buffer. 0xd0 buffered program confirm the confirm command is issued after th e data streaming for writing into the buffer is done. this instructs the wsm to perform the buffered program algorithm, writing the data from th e buffer to the flash memory array. 0x80 befp setup first cycle of a 2-cycle command; initiates the befp mode. the cui then waits for the befp confirm command , 0xd0, that initiates the befp algorithm. all other commands are ignored when befp mode begins. 0xd0 befp confirm if the previous command was befp setup (0x80), the cui latches the address and data, and prepares the device for befp mode. erase 0x20 block erase setup first cycle of a 2-cycle command; prepares the cui for a block-erase operation. the wsm performs the erase algorithm on the block addressed by the erase confirm command. 0xd0 block erase confirm if the first command was block erase setup (0x20), the cui latches the address and data, and the wsm erases the addressed block. during block- erase operations, the device responds only to read status register and erase suspend commands. ce# or oe# must be toggled to update the status register in asynchronous read. ce# or adv# must be toggled to update the sr data for synchronous non-array reads.
p30-65nm sbc datasheet apr 2010 20 order number: 208033-02 6.2 device command bus cycles device operations are initiated by writing specific device commands to the cui. see table 7, ?command bus cycles? on page 21 . several commands are used to modify array data including word program and block erase commands. writing either command to the cui initiates a sequence of internally - timed functions that culminate in the completion of the requested task. howeve r, the operation can be aborted by either asserting rst# or by issuing an appropriate suspend command. suspend 0xb0 program or erase suspend this command issued to any device address initiates a suspend of the currently-executing program or block erase operation. the status register indicates successful suspend operation by setting either sr.2 (program suspended) or sr.6 (erase suspended), along with sr.7 (ready). the wsm remains in the suspend mode regardless of control signal states (except for rst# asserted). 0xd0 suspend resume this command issued to any device address resumes the suspended program or block-erase operation. protection 0x60 block lock setup first cycle of a 2-cycle command; prepares the cui for block lock configuration changes. 0x01 block lock if the previous command was block lock setup (0x60), the addressed block is locked. 0xd0 block unlock if the previous command was block lock setup (0x60), the addressed block is unlocked. if the addressed block is in a lock-down state, the operation has no effect. 0x2f block lock-down if the previous command was block lock setup (0x60), the addressed block is locked down. 0xc0 otp register or lock register program setup first cycle of a 2-cycle command; prepares the device for a otp register or lock register program operation. the second cycle latches the register address and data, and starts the prog ramming algorithm to program data into the otp array. configuration 0x60 read configuration register setup first cycle of a 2-cycle command; prepares the cui for device read configuration. 0x03 read configuration register if the previous command was read configuration register setup (0x60), the cui latches the address and writes a[16:1] to the read configuration register. following a configure rcr command, subsequent read operations access array data. blank check 0xbc block blank check first cycle of a 2-cycle command; initiates the blank check operation on a array block. 0xd0 block blank check confirm second cycle of blank check command sequence; it latches the block address and executes blank check on the array block. efi 0xeb extended function interface this command is used in extended function interface. first cycle of a multiple- cycle command second cycle is a sub-op-code, the data written on third cycle is one less than the word count; the allowable value on this cycle are 0 through 511. the subsequent cycles load data words into the program buffer at a specified address unt il word count is achieved. table 6: command codes and definitions (sheet 2 of 2) mode code device mode description
datasheet apr 2010 21 order number:208033-02 p30-65nm sbc table 7: command bus cycles mode command bus cycles first bus cycle second bus cycle oper addr (1) data (2) oper addr (1) data (2) read read array 1 write dna 0xff - - - read device identifier 2 write dna 0x90 read dba + ia id read cfi 2writedna0x98readdba + cfi-acfi-d read status register 2 write dna 0x70 read dna srd clear status register 1 write dna 0x50 - - - program word program 2 write wa 0x40 write wa wd buffered program (3) > 2 write wa 0xe8 write wa n - 1 buffered enhanced factory program (befp) (4) > 2 write wa 0x80 write wa 0xd0 erase block erase 2 write ba 0x20 write ba 0xd0 suspend program/erase suspend 1writedna0xb0 - - - program/erase resume 1writedna0xd0- - - protection block lock 2 write ba 0x60 write ba 0x01 block unlock 2 write ba 0x60 write ba 0xd0 block lock-down 2 write ba 0x60 write ba 0x2f program otp register 2 write otp-ra 0xc0 write otp-ra otp-d program lock register 2 write lra 0xc0 write lra lrd configuration configure read configuration register 2 write rcd 0x60 write rcd 0x03 blank check block blank check 2 write ba 0xbc write ba d0 efi extended function interface (5) >2 write wa 0xeb write wa sub-op code notes: 1. first command cycle address should be the same as the operation?s target address. dba = device base address. dna = address within the device. ia = identification code address offset. cfi-a = read cfi address offset. wa = word address of memory location to be written. ba = address within the block. otp-ra = otp register address. lra = lock register address. rcd = read configuration register data on a[16:1] fo r tsop and bga package; on a[15:0] for quad+ package. 2. id = identifier data. cfi-d = cfi data on dq[15:0]. srd = status register data. wd = word data. n = word count of data to be loaded into the write buffer. otp-d = otp register data. lrd = lock register data. 3. the second cycle of the buffered program command is the word count of the data to be loaded into the write buffer. this is followed by up to 256 words of data. then the confirm command (0xd0) is issued, trig gering the array programming operation. 4. the confirm command (0xd0) is followed by the buffer data. 5. the second cycle is a sub-op-code, the data written on third cycle is n-1; 1 n 256. the subsequent cycles load data words into the program buffer at a specified address until word count is achieved. after the data words are loaded, the final cycle is the confirm cycle 0xd0).
p30-65nm sbc datasheet apr 2010 22 order number: 208033-02 7.0 read operation the device can be in any of four read states: read array, read identifier, read status or read query. upon power-up or after a reset, the device defaults to read array mode. to change the read state, the approp riate read command must be written to the device (see section 6.2, ?device command bus cycles? on page 20 ). the following sections describe read-mode operations in detail. in order to enable synchronous burst reads, the rcr must be configured. please see section 11.2, ?read configuration register (rcr)? on page 34 for rcr detail. please refer to section 5.1, ?read - asynchronous mode? on page 16 and section 5.2, ?read - synchronous mode? on page 16 for bus operation detail. see section 25, ?ac read specifications? on page 50 for timing specification. 7.1 read array following a device power-up or reset, the device is set to read array mode. however, to perform array reads after any other device operation (e.g. write operation), the read array command must be issued in order to read from the flash memory array. please refer to section 5.1, ?read - asynchronous mode? on page 16 and section 5.2, ?read - synchronous mode? on page 16 for bus operation detail. see section 25, ?ac read specifications? on page 50 for timing specification. 7.2 read device identifier the read device identifier command instructs the device to output manufacturer code, device identifier code, block-lock status, otp register data, or read configuration register data (see section 6.2, ?device command bus cycles? on page 20 for details on issuing the read device identifier command). table 8, ?device identifier information? on page 22 and table 9, ?device id codes? on page 23 show the address offsets and data values for this device. table 8: device identifier information (sheet 1 of 2) item address (1,2) data(x16) manufacturer code 0x00 0x89h device id code 0x01 id (see ta b l e 9 ) block lock configuration: bba (1) + 0x02 lock bit: ? block is unlocked dq0 = 0b0 ? block is locked dq0 = 0b1 ? block is not locked-down dq1 = 0b0 ? block is locked-down dq1 = 0b1 read configuration register 0x05 rcr contents general purpose register (3) dba (2) + 0x07 gpr data lock register 0 0x80 pr-lk0 64-bit factory-programmed otp register 0x81?0x84 numonyx factory otp register data 64-bit user-programmable otp register 0x85?0x88 user otp register data
datasheet apr 2010 23 order number:208033-02 p30-65nm sbc 7.3 read cfi the read cfi command instructs the device to output common flash interface data when read. see figure 6.1, ?device command codes? on page 19 . section a.1, ?common flash interface? on page 61 shows cfi information and address offsets within the cfi database. 7.4 read status register to read the status register, issue the read status register command at any address. status register information is available to which the read status register, word program, or block erase command was issued. srd is automatically made available following a word program, block erase, or block lock command sequence. reads from the device after any of these command sequ ences outputs the device?s status until another valid command is written (e.g. the read array command). the status register is read using single asynchronous-mode or synchronous burst mode reads. srd is output on dq[7:0], while 0x00 is output on dq[15:8]. in asynchronous mode the falling edge of oe#, or ce# (whichever occurs first) updates and latches the status register contents. however, when reading the status register in synchronous burst mode, ce# or adv# must be toggled to update srd. the device ready status bit (sr.7) provides overall status of the device. sr[6:1] present status and error information about the program, erase, suspend, vpp, and block-locked operations. see table 12, ?status register description? on page 34 for the description of the status register. 7.5 clear status register the clear status register command clears th e status register. it functions independent of vpp. the wsm sets and clears sr.7, but it sets bits sr[5:3,1] without clearing them. the status register should be cleared before starting a command sequence to avoid any ambiguity. a device reset also clears the status register. lock register 1 0x89 pr-lk1 otp register lock data 128-bit user-programmable otp registers 0x8a?0x109 user otp register data notes: 1. bba = block base address. 2. dba = device base address, numonyx reserves other configuration address locations. 3. the gpr is used as read out register for extended function interface command. table 9: device id codes id code type device density device identifier codes to p b o o t 64-mbit 8817 128-mbit 8818 bottom boot 64-mbit 881a 128-mbit 881b table 8: device identifier in formation (sheet 2 of 2) item address (1,2) data(x16)
p30-65nm sbc datasheet apr 2010 24 order number: 208033-02 8.0 program operation the device supports three programming methods: word programming (40h/10h), buffered programming (e8h, d0h), and buff ered enhanced factory programming (80h, d0h). the following sections describe device programming in detail. successful programming requires the addressed block to be unlocked. if the block is locked down, wp# must be deasserted and the block must be unlocked before attempting to program the block. attempti ng to program a locked block causes a program error (sr[4,1] set) and termination of the operation. see section 10.0, ?security? on page 31 for details on locking and unlocking blocks. 8.1 word programming word programming operations are initia ted by writing the word program setup command to the device. this is followed by a second write to the device with the address and data to be programmed. the device outputs status register data when read. see figure 32, ?word program flowchart? on page 73 . vpp must be above v pplk , and within the specified v ppl min/max values. during programming, the wsm executes a sequence of internally-timed events that program the desired data bits at the addresse d location, and verifies that the bits are sufficiently programmed. programming the flash memory array changes ?ones? to ?zeros?. memory array bits that are zeros ca n be changed to ones only by erasing the block. the status register can be examined for programming progress and errors by reading at any address. the device remains in the read status register state until another command is written to the device. status register bit sr.7 indicates the programming status while the sequence executes. commands that can be issued to the device during programming are read status register, read device identifier, read cfi, and read array (this returns unknown data). when programming has finished, status register bit sr.4 (when set) indicates a programming failure. if sr.3 is set, the wsm could not perform the word programming operation because vpp was outside of its acce ptable limits. if sr.1 is set, the word programming operation attempted to program a locked block, causing the operation to abort. before issuing a new command, the status register contents should be examined and then cleared using the clear status register command. any valid command can follow, when word programming has completed. 8.2 buffered programming the device features a 256-word buffer to enable optimum programming performance. for buffered programming, data is first written to an on-chip write buffer. then the buffer data is programmed into the flash memory array in buffer-size increments. this can improve system programming perfor mance significantly over non-buffered programming. (see figure 35, ?buffer program flowchart? on page 76 ). when the buffered programming setup command is issued, status register information is updated and reflects the availability of the buffer. sr.7 indicates buffer availability: if set, the buffer is available; if cleared, the buffer is not available. note: the device defaults to output sr data after the buffered programming setup command (e8h) is issued. ce# or oe# must be toggled to update status register. don?t issue the
datasheet apr 2010 25 order number:208033-02 p30-65nm sbc read sr command (70h), which would be inte rpreted by the internal state machines as buffer word count. on the next write, a word count is written to the device at the buffer address. this tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. on the next write, a device start address is given along with the first data to be written to the flash memory array. subsequent writ es provide additional device addresses and data. all data addresses must lie within the start address plus the word count. optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 256-word boundary (a[8:1] = 0x00). note: if a misaligned address range is issued during buffered programming, the program region must also be within an 256-word aligned boundary. after the last data is written to the buffer, the buffered programming confirm command must be issued to the original block address. the wsm begins to program buffer contents to the flash memory array. if an error occurs while writing to the array, the device stops programming, and sr[7,4] ar e set, indicating a programming failure. when buffered programming has completed, additional buffer writes can be initiated by issuing another buffered programming se tup command and repeating the buffered program sequence. buffered programming may be performed with vpp = v ppl or v pph (see section 13.2, ?operating conditions? on page 45 for limitations when operating the device with vpp = v pph ). if an attempt is made to program past an erase-block boundary using the buffered program command, the device aborts the operation. this generates a command sequence error, and sr[5,4] are set. if buffered programming is attempted while vpp is at or below v pplk , sr[4,3] are set. if any errors are detected that have set status register bits, the status register should be cleared using the clear status register command. 8.3 buffered enhanced factory programming buffered enhanced factory programing (befp) speeds up the flash programming perforamnce. the enhanced programming algori thm used in befp eliminates traditional programming elements that drive up overhead in device programmer systems. befp consists of three phases: setup, program/verify, and exit (see figure 37, ?befp flowchart? on page 78 ). it uses a write buffer to spread up the program performance across 256 data words. verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. a single two-cycle command sequence programs the entire block of data. this enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 256 data words. host pr ogrammer bus cycles fill the device?s write buffer followed by a status check. sr.0 indicates when data from the buffer has been programmed into sequential flash memory array locations. following the buffer-to-flash array programming sequence, the write state machine (wsm) increments internal addressing to au tomatically select the next 256-word array boundary. this aspect of befp saves host programming equipment the address-bus setup overhead. with adequate continuity testing, prog ramming equipment can rely on the wsm?s internal verification to ensure that the devi ce has programmed properly. this eliminates the external post-program verification and its associated overhead.
p30-65nm sbc datasheet apr 2010 26 order number: 208033-02 8.3.1 befp requirements and considerations note: word buffer boundaries in the array are determined by a[8:1] (0x00 through 0xff). the alignment start point is a[8:1] = 0x000. notes: 1. some degradation in performance may oc cur is this limit is exceeded, but the internal algorithm continues to work properly. 2. if the internal address counter increments beyond the block?s maximum address, addressing wraps around to the beginning of the block. 3. if the number of words is less than 256, remaining locations must be filled with 0xffff. 8.3.2 befp setup phase after receiving the befp se tup and confirm command sequ ence, status register bit sr.7 (ready) is cleared, indicating that the wsm is busy with befp algorithm startup. a delay before checking sr.7 is required to allow the wsm enough time to perform all of its setups and checks (block-lock status, vpp le vel, etc.). if an error is detected, sr.4 is set and befp operation terminates. if the block was found to be locked, sr.1 is also set. sr.3 is set if the error occurred due to an incorrect vpp level. note: reading from the device after the befp se tup and confirm command sequence outputs status register data. do not issue the read status register command; it will be interpreted as data to be loaded into the buffer. 8.3.3 befp program/verify phase after the befp setup phase has completed, the host programming system must check sr[7,0] to determine the availability of the write buffer for data streaming. sr.7 cleared indicates the device is busy and th e befp program/verify phase is activated. sr.0 indicates the write buffer is available. table 10: befp requirements parameter/issue requirement notes case temperature t c = 30 c 10c - vcc nominal vcc - vpp driven to v pph - setup and confirm target block must be unlocked before issuing the befp setup and confirm commands. - programming the first-word address (wa0) of the block to be programmed must be held constant from the setup phase through all data stream ing into the target block, until transition to the exit phase is desired. - buffer alignment wa0 must align with the start of an array buffer boundary. 1 table 11: befp considerations parameter/issue requirement notes cycling for optimum performance, cycling must be limited below 50 erase cycles per block. 1 programming blocks befp programs one block at a time ; all buffer data must fall within a single block. 2 suspend befp cannot be suspended. - programming the flash memory array programming to the flash memory array can occur only when the buffer is full. 3
datasheet apr 2010 27 order number:208033-02 p30-65nm sbc two basic sequences repeat in this phase: lo ading of the write buffer, followed by buffer data programming to the array. for befp, the count value for buffer loading is always the maximum buffer size of 256 words. duri ng the buffer-loading sequence, data is stored to sequential buffer locations star ting at address 0x00. programming of the buffer contents to the flash memory array starts as soon as the buffer is full. if the number of words is less than 256, the rema ining buffer locations must be filled with 0xffff . caution: the buffer must be comple tely filled for pr ogramming to occu r. supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. any data previously loaded into the buffer during the fill cycle is not programmed into the array. the starting address for data entry must be buffer size aligned, if not the befp algorithm will be aborted and the program fails and (sr.4) flag will be set. data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. the host programming system must poll sr.0 to determine when the buffer program sequence completes. sr.0 cleared indicates that all buffer data has been transferred to the flash array; sr.0 set indica tes that the buffer is not available yet for the next fill cycle. the host system may check full status for errors at any time, but it is only necessary on a block basis after befp exit. after the buffer fill cycle, no write cycles should be issued to the device until sr.0 = 0 and the device is ready for the next buffer fill. note: any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. the host programming system continues the befp algorithm by providing the next group of data words to be written to the buffer. alternatively, it can terminate this phase by changing the block address to one outside of the current block?s range. the program/verify phase concludes when the programmer writes to a different block address; data supplied must be 0xffff. upon program/verify phase completion, the device enters the befp exit phase. 8.3.4 befp exit phase when sr.7 is set, the device has returned to normal operating conditions. a full status check should be performed at this time to ensure the entire block programmed successfully. when exiting the befp algorithm with a block address change, the read mode will not change. after befp exit, any va lid command can be issued to the device. 8.4 program suspend issuing the program suspend command while programming suspends the programming operation. this allows data to be accessed from the device other than the one being programmed. the program suspend command can be issued to any device address. a program operation can be suspended to perform reads only. additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see figure 36, ?program suspend/resume flowchart? on page 77 ). when a programming operation is executin g, issuing the program suspend command requests the wsm to suspend the programming algorithm at predetermined points. the device continues to output status register data after the program suspend command is issued. programming is suspended when status register bits sr[7,2] are set. suspend latency is specified in section 15.5, ?program and erase characteristics? on page 58 .
p30-65nm sbc datasheet apr 2010 28 order number: 208033-02 to read data from the device, the read array command must be issued. read array, read status register, read device identifi er, read cfi, and program resume are valid commands during a program suspend. during a program suspend, deasserting ce# places the device in standby, reducing active current. vpp must remain at its programming level, and wp# must remain unchanged while in program suspend. if rst# is asserted, the device is reset. 8.5 program resume the resume command instructs the device to continue programming, and automatically clears status register bits sr[7,2]. this command can be written to any address. if error bits are set, the status re gister should be cleared before issuing the next instruction. rst# must remain deasserted (see figure 33, ?program suspend/ resume flowchart? on page 74 ). 8.6 program protection when vpp = v il , absolute hardware write protection is provided for all device blocks. if vpp is at or below v pplk , programming operations halt an d sr.3 is set indicating a vpp- level error. block lock registers are not affe cted by the voltage level on vpp; they may still be programmed and read, even if vpp is less than v pplk . figure 8: example vpp supply connections ? factory programming with v pp = v pph ? complete write/erase protection when v pp v pplk vcc vpp vcc vpp ? low voltage and factory programming ? low-voltage programming only ? logic control of device protection vcc vpp ? low voltage programming only ? full device protection unavailable vcc vpp 10k v pp v cc v cc prot # v cc v pp =v pph v cc
datasheet apr 2010 29 order number:208033-02 p30-65nm sbc 9.0 erase operation flash erasing is performed on a block basis. an entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. when a block is erased, all bits within that block read as logical ones. the following sections describe block erase operations in detail. 9.1 block erase block erase operations are initiated by wr iting the block erase setup command to the address of the block to be erased (see section 6.2, ?device command bus cycles? on page 20 ). next, the block erase confirm comman d is written to the address of the block to be erased. if the device is placed in standby (ce# deasserted) during an erase operation, the device completes the erase operation before entering standby. vpp must be above v pplk and the block must be unlocked (see figure 38, ?block erase flowchart? on page 79 ). during a block erase, the wsm executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. erasing the flash memory array changes ?zeros? to ?ones?. memory block array data that are ones can be changed to zeros by programming block. the status register can be examined for block erase progress and errors by reading any address. the device remains in the read status register state until another command is written. sr.0 indicates whethe r the addressed block is erasing. status register bit sr.7 is set upon erase completion. status register bit sr.7 indicates block erase status while the sequence executes. when the erase operation has finished, status register bit sr.5 indicates an erase failure if set. sr.3 set would indicate that the wsm could not perform the erase operation because vpp was outside of its acce ptable limits. sr.1 set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. before issuing a new command, the status re gister contents should be examined and then cleared using the clear status register command. any valid command can follow once the block erase operation has completed. 9.2 blank check the blank check operation determines whether a specified array block is blank (i.e. completely erased). without blank check, bl ock erase would be the only other way to ensure a block is completely erased. blank ch eck is especially useful in the case of erase operation interrupted by a power loss event. blank check can apply to only one block at a time, and no operations other than status register reads are allowed during blank check (e.g. reading array data, program, erase etc). suspend and resume operations are not supported during blank check, nor is blank check supported during any suspended operations. blank check operations are initiated by wr iting the block blank check command to the block address. next, the blank check confirm command is issued along with the same block address. when a successful comman d sequence is entered, the device automatically enters the read status state. the wsm then reads the entire specified block, and determines whether any bit in the block is programmed or over-erased. the status register can be examined for blank check progress and errors by reading any address within the block being accessed. during a blank check operation, the status register indicates a busy status (sr.7 = 0). upon completion, the status
p30-65nm sbc datasheet apr 2010 30 order number: 208033-02 register indicates a ready status (sr.7 = 1). the status register should be checked for any errors, and then cleared. if the blank check operation fails, which means the block is not completely erased, the status regist er bit sr.5 will be set (?1?). ce# or oe# toggle (during polling) updates the status register. after examining the status register, it should be cleared by the clear status register command before issuing a new command. the device remains in status register mode until another command is written to the device. any command can follow once the blank check command is complete. 9.3 erase suspend issuing the erase suspend command while erasing suspends the block erase operation. this allows data to be accessed from memory locations other than the one being erased. the erase suspend command can be issued to any device address. a block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see figure 34, ?erase suspend/resume flowchart? on page 75 ). when a block erase operation is executing, issuing the erase suspend command requests the wsm to suspend the erase algorithm at predetermined points. the device continues to output status register data after the erase suspend command is issued. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 15.5, ?program and erase characteristics? on page 58 . to read data from the device (other than an erase-suspended block), the read array command must be issued. during erase su spend, a program command can be issued to any block other than the erase-suspende d block. block erase cannot resume until program operations initiated during erase su spend complete. read array, read status register, read device identifier, read cf i, and erase resume are valid commands during erase suspend. additionally, clear status register, program, program suspend, block lock, block unlock, and block lock-down are valid commands during erase suspend. during an erase suspend, deasserting ce# places the device in standby, reducing active current. vpp must remain at a va lid level, and wp# mu st remain unchanged while in erase suspend. if rst# is asserted, the device is reset. 9.4 erase resume the erase resume command instructs the device to continue erasing, and automatically clears sr[7,6]. this command can be written to any address. if status register error bits are set, the status register should be cleared before issuing the next instruction. rst# must remain deasserted. 9.5 erase protection when vpp = v il , absolute hardware erase protection is provided for all device blocks. if vpp v pplk , erase operations halt and sr.3 is set indicating a vpp-level error.
datasheet apr 2010 31 order number:208033-02 p30-65nm sbc 10.0 security the device features security modes used to protect the information stored in the flash memory array. the following sections describe each security mode in detail. 10.1 block locking individual instant block locking is used to protect user code and/or data within the flash memory array. all blocks power up in a locked state to protect array data from being altered during power transitions. any block ca n be locked or unlocked with no latency. locked blocks cannot be programmed or erased; they can only be read. software-controlled security is implemente d using the block lock and block unlock commands. hardware-controlled security can be implemented using the block lock- down command along with asserting wp#. also, vpp data security can be used to inhibit program and erase operations (see section 8.6, ?program protection? on page 28 and section 9.5, ?erase protection? on page 30 ). 10.1.1 lock block to lock a block, issue the block lock setu p command. the next command must be the block lock command issued to the desired block?s address (see section 6.2, ?device command bus cycles? on page 20 and figure 39, ?block lock operations flowchart? on page 80 ). if the configure read configuration register command is issued after the block lock setup command, the device configures the rcr instead. block lock and unlock operations are not affect ed by the voltage level on vpp. the block lock bits may be modified and/or re ad even if vpp is at or below v pplk . 10.1.2 unlock block the block unlock command is used to unlock blocks (see section 6.2, ?device command bus cycles? on page 20 ). unlocked blocks can be read, programmed, and erased. unlocked blocks return to a locked state when the device is reset or powered down. if a block is in a lock-down state, wp# must be deasserted before it can be unlocked (see figure 9, ?block locking state diagram? on page 32 ). 10.1.3 lock-down block a locked or unlocked block can be locked-down by writing the block lock-down command sequence (see section 6.2, ?device command bus cycles? on page 20 ). blocks in a lock-down state cannot be prog rammed or erased; they can only be read. however, unlike locked blocks, their locked state cannot be changed by software commands alone. a locked-down block can on ly be unlocked by issuing the block unlock command with wp# deasserted. to return an unlocked block to locked-down state, a block lock-down command must be issued prior to changing wp# to v il . locked-down blocks revert to the locked state upon reset or power up the device (see figure 9, ?block locking state diagram? on page 32 ). 10.1.4 block lock status the read device identifier command is used to determine a block?s lock status (see section 7.2, ?read device identifier? on page 22 ). data bits dq[1:0] display the addressed block?s lock status; dq0 is the addressed block?s lock bit, while dq1 is the addressed block?s lock-down bit.
p30-65nm sbc datasheet apr 2010 32 order number: 208033-02 note: lk: lock setup command, 60h; lk/d0h: unlock command; lk/01h: lock command; lk/2fh: lock-down command. 10.1.5 block locking during suspend block lock and unlock changes can be performed during an erase suspend. to change block locking during an erase operation, first issue the erase suspend command. monitor the status register until sr.7 and sr.6 are set, indicating the device is suspended and ready to accept another command. next, write the desired lock command sequence to a block, which changes the lock state of that block. after completing block lock or unlock operations, resume the erase operation using the erase resume command. note: a lock block setup command followed by any command other than lock block, unlock block, or lock-down block produces a command sequence error and set status register bits sr.4 and sr.5. if a command sequence error occurs during an erase suspend, sr.4 and sr.5 remains set, even after the erase operation is resumed. unless the status register is cleared using the clear status register command before resuming the erase operation, possible eras e errors may be masked by the command sequence error. if a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. however, the erase operation completes when it is resumed. block lock operations cannot occur during a program suspend. see appendix a, ?write state machine? on page 83 , which shows valid commands during an erase suspend. figure 9: block locking state diagram [000 ] [001 ] [011 ] [111 ] [101 ] [110 ] [100 ] lk/ d0h lk/ 01h lk/ 2fh l k / 2 f h lk/ d0h lk/ 01h or 2fh lk/ d0h lk/ 01h lk/ 2fh lk/ 2fh pgm/erase allowed pgm/erase prevented wp# = v il = 0 wp# = v ih = 1 power-up/ reset default power-up/ reset default locked-down locked-down is d isab led b y wp# = v ih v irtu al lo ck- down any lock com m ands wp# toggle w p # t o g g l e [010]
datasheet apr 2010 33 order number:208033-02 p30-65nm sbc 10.2 selectable otp blocks p30-65nm sbc device is backward-compatible with the otp permanent block lock security feature of the legacy p30-130nm device. blocks from the main array can be optionally configured as otp. ask your local numonyx sales representative for details about these selectable otp implementations. 10.3 password access the password access is a security enhancement offered on the p30-65nm sbc device. this feature protects information stored in array blocks by preventing content alteration or reads until a valid 64-bit password is received. the password access may be combined with flexible block blocking to create a multi-tiered solution. please contact representative numonyx sales for further details concerning the password access.
p30-65nm sbc datasheet apr 2010 34 order number: 208033-02 11.0 register when non-array reads are performed in asynch ronous page mode only the first data is valid and all subsequent data are undefined. when a non-array read operation occurs as synchronous burst mode, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. 11.1 status register (sr) the status register provides the ready/busy information of the device, as well as the error information about the program, erase, vpp and block-locked operations. please refer to section 7.4, ?read status register? on page 23 and section 7.5, ?clear status register? on page 23 for detail operations. 11.2 read configuration register (rcr) the rcr is a 16-bit read/write register used to select bus-read mode (synchronous or asynchronous), and to configure synchronous burst read characteristics of the device. to modify rcr settings, use the configure read configuration register command (see section 6.2, ?device command bus cycles? on page 20 ). table 12: status register description status register (sr) default value = 0x80 device ready status erase suspend status 1 1. always clear the status register before resuming erase operat ions afer an erase suspend command; this prevents ambiguity in status register information. for example, if a command sequence error occurs during an erase suspend state, the status register contains the command sequence error status (sr[7,5,4] set). when the erase operation resumes and finishes, possible errors during the erase operation cannot be deteted via the st auts register because it contains the previous error status. erase status program status vpp status program suspend status block-locked status befp write status drs ess es ps vpps pss bls bws 76 5 4 3 2 1 0 bit name description 7 device ready status 0 = device is busy; program or erase cycle in progress; sr.0 valid. 1 = device is ready; sr[6:1] are valid. 6 erase suspend status 0 = erase suspend not in effect. 1 = erase suspend in effect. 5erase status command sequence error sr.5 sr.4 description 4 program status 0 0 1 1 0 1 0 1 program or erase operation successful. program error - operation aborted. erase error - operation aborted. command sequence erro r - command aborted. 3 vpp status 0 = vpp within acceptable limits du ring program or erase operation. 1 = vpp < v pplk during program or erase operation. 2 program suspend status 0 = program suspend not in effect. 1 = program suspend in effect. 1 block-locked status 0 = block not locked during program or erase. 1 = block locked during program or erase; operation aborted. 0befp write status 2 2. befp mode is only valid in array. after buffered enhanced factory programming (befp) data is loaded into the buffer: 0 = befp complete. 1 = befp in-progress.
datasheet apr 2010 35 order number:208033-02 p30-65nm sbc rcr contents can be examined using the re ad device identifier command, and then reading from offset 0x05 (see section 7.2, ?read device identifier? on page 22 ). upon power-up or exit from reset, th e rcr defaults to asynchronous mode. the rcr is shown in ta b l e 1 3 . the following sections describe each rcr bit function. 11.2.1 read mode (rcr.15) the read mode (rm) bit selects synchronous burst-mode or asynchronous page-mode operation for the device. when the rm bit is set, asynchronous page mode is selected (default). when rm is cleared, synchronous burst mode is selected. table 13: read configuratio n register description read configuration register (rcr) read mode res latency count wait polarity data output config wait delay burst seq clk edge res res burst wrap burst length rm r lc[3:0] wp doc wd bs ce r r bw bl[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name description 15 read mode (rm) 0 = synchronous burst-mode read 1 = asynchronous page-mode read (default) 14 reserved (r) set to 0. this bit cannot be altered by customer. 13:11 latency count (lc[2:0]) 000 =code 0 reserved 001 =code 1 reserved 010 =code 2 011 =code 3 100 =code 4 101 =code 5 110 =code 6 111 =code 7(default) 10 wait polarity (wp) 0 =wait signal is active low 1 =wait signal is active high (default) 9 data output configuration (doc) 0 =data held for a 1-clock data cycle 1 =data held for a 2-clock data cycle (default) 8 wait delay (wd) 0 =wait deasserted with valid data 1 =wait deasserted one data cycle before valid data (default) 7 burst sequence (bs) 0 =reserved 1 =linear (default) 6 clock edge (ce) 0 = falling edge 1 = rising edge (default) 5:4 reserved (r) set to 0. this bit cannot be altered by customer. 3 burst wrap (bw) 0 =wrap; burst accesses wrap within burst length set by bl[2:0] 1 =no wrap; burst accesses do not wrap within burst length (default) 2:0 burst length (bl[2:0]) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =continuous-word burst (default) (other bit settings are reserved)
p30-65nm sbc datasheet apr 2010 36 order number: 208033-02 11.2.2 latency count (rcr[13:11]) the latency count (lc) bits tell the device ho w many clock cycles must elapse from the rising edge of adv# (or from the first vali d clock edge after adv# is asserted) until the first valid data word is driven onto dq[15:0]. the input clock frequency is used to determine this value and figure 10 shows the data output latency for the different settings of lc. the maximum latency count for p30-65nm sbc device would be code 4 based on the max clock frequency specificat ion of 52mhz, and there will be zero wait states when bursting within the word line. please also refer to section 11.2.3, ?end of word line (eowl) considerations? on page 37 for more information on eowl. refer to table 14, ?lc and frequency support? on page 36 for latency code settings. figure 10: first-access latency count table 14: lc and frequency support latency count settings frequency support (mhz) 3 40 4 52 code 1 (reserved code 6 code 5 code 4 code 3 code 2 code 0 (reserved) code 7 valid address valid output valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid output valid out put valid output valid output valid output valid output valid out put valid output valid output valid output valid out put valid output valid output valid out put valid output valid out put valid output valid output address [a] adv# [v] dq 15-0 [d/q] clk [c] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q] dq 15-0 [d/q]
datasheet apr 2010 37 order number:208033-02 p30-65nm sbc 11.2.3 end of word line (eowl) considerations the delay may occur when a burst sequence access crosses a 8-word boundary. that is, a[3:1] of start address does not equal 0x0. figure 12, ?end of wordline timing diagram? on page 37 illustrates the end of wordline wait state(s), which occur after the first 8-word boundary is reached. the number of data words and the number of wait states is summarized in table 15, ?end of wordline data and wait state comparison? on page 38 for both p30-130nm and p30-65nm sbc devices. figure 11: example latency count setting using code 3 clk ce# adv# a[max:0] d[15:0] t data code 3 address data 012 34 r103 high-z a[max:1] figure 12: end of wordline timing diagram a[max:1] adv# oe# wait dq[15:0] data data data eowl clk latency count
p30-65nm sbc datasheet apr 2010 38 order number: 208033-02 table 15: e nd of wordline data and wait state comparison 11.2.4 wait polarity (rcr.10) the wait polarity bit (wp), rcr.10 determines the asserted level (v oh or v ol ) of wait. when wp is set, wait is asserted high. wh en wp is cleared, wait is asserted low (default). wait changes state on valid cl ock edges during active bus cycles (ce# asserted, oe# asserted, rst# deasserted). 11.2.5 data output configuration (rcr.9) the data output configuration (doc) bit, rcr.9 determines whether a data word remains valid on the data bus for one or two clock cycles. this peri od of time is called the ?data cycle?. when doc is set, output data is held for two clocks (default). when doc is cleared, output data is held for one clock (see figure 13, ?data hold timing? on page 39 ). the processor?s data setup time and the flash memory?s clock-to-data output delay should be considered when determinin g whether to hold output data for one or two clocks. a method for determining the da ta hold configuration is shown below: to set the device at one clock data hold fo r subsequent reads, the following condition must be satisfied: t chqv (ns) + t data (ns) one clk period (ns) t data = data set up to clock (defined by cpu) for example, with a clock frequency of 40 mhz, the clock period is 25 ns. assuming t chqv = 20 ns and t data = 4 ns. applying these values to the formula above: 20 ns + 4 ns 25 ns the equation is satisfied and data will be available at every clock period with data hold setting at one clock. if t chqv (ns) + t data (ns) > one clk period (ns), data hold setting of 2 clock periods must be used. latency count p30-130nm p30-65nm sbc data states wait states data states wait states 1 not supported not supported not supported not supported 2 4 0 to 1 not supported not supported 3 4 0 to 2 8 0 to 2 4 4 0 to 3 8 0 to 3 5 4 0 to 4 8 0 to 4 6 4 0 to 5 8 0 to 5 7 4 0 to 6 8 0 to 6 table 16: wait functionality table condition wait notes ce# = ?1?, oe# = ?x? or ce# = ?0?, oe# = ?1? high-z 1 ce# =?0?, oe# = ?0? active 1 synchronous array reads active 1 synchronous non-array reads active 1 all asynchronous reads deasserted 1 all writes high-z 1,2 notes: 1. active: wait is asserted until data becomes valid, then deasserts. 2. when oe# = v ih during writes, wait = high-z.
datasheet apr 2010 39 order number:208033-02 p30-65nm sbc 11.2.6 wait delay (rcr.8) the wait delay (wd) bit controls the wait assertion-delay behavior during synchronous burst reads. wait can be asserted either during or one data cycle before valid data is output on dq[15:0]. when wd is set, wait is deasserted one data cycle before valid data (default). when wd is cleared, wait is deasserted during valid data. 11.2.7 burst sequence (rcr.7) the burst sequence (bs) bit selects linear-bu rst sequence (default). only linear-burst sequence is supported. ta b l e 1 7 shows the synchronous burst sequence for all burst lengths, as well as the effect of the burst wrap (bw) setting. figure 13: data hold timing valid output valid output valid output valid output valid output clk [c] d[15:0] [q] d[15:0] [q] 2 clk data hold 1 clk data hold table 17: burst sequence word ordering (s heet 1 of 2) start addr. (dec) burst wrap (rcr.3) burst addressing sequence (dec) 4-word burst (bl[2:0] = 0b001) 8-word burst (bl[2:0] = 0b010) 16-word burst (bl[2:0] = 0b011) continuous burst (bl[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-? 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5?15-0 1-2-3-4-5-6-7-? 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6?15-0-1 2-3-4-5-6-7-8-? 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7?15-0-1-2 3-4-5-6-7-8-9-? 40 4-5-6-7-0-1-2-3 4-5-6-7-8?15-0-1-2-3 4-5-6-7-8-9-10? 50 5-6-7-0-1-2-3-4 5-6-7-8-9?15-0-1-2-3- 4 5-6-7-8-9-10-11? 60 6-7-0-1-2-3-4-5 6-7-8-9-10?15-0-1-2- 3-4-5 6-7-8-9-10-11-12-? 70 7-0-1-2-3-4-5-6 7-8-9-10?15-0-1-2-3- 4-5-6 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 0 14-15-0-1-2?12-13 14-15-16-17-18-19-20- ? 15 0 15-0-1-2-3?13-14 15-16-17-18-19-20-21- ? ? ? ? ? ? ? 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4?14-15 0-1-2-3-4-5-6-?
p30-65nm sbc datasheet apr 2010 40 order number: 208033-02 11.2.8 clock edge (rcr.6) the clock edge (ce) bit selects either a risi ng (default) or falling clock edge for clk. this clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert wait. 11.2.9 burst wrap (rcr.3) the burst wrap (bw) bit determines whethe r 4, 8, or 16-word burst length accesses wrap within the selected word-length bo undaries or cross word-length boundaries. when bw is set, burst wrapping does not occur (default). when bw is cleared, burst wrapping occurs. 11.2.10 burst length (rcr[2:0]) the burst length bits (bl[2:0]) select the linear burst length for all synchronous burst reads of the flash memory array. the burst lengths are 4-word, 8-word, 16-word or continuous word. continuous burst accesses are linear only, an d do not wrap within any word length boundaries (see table 17, ?burst sequence word ordering? on page 39 ). when a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the ?burstable? address space. 11.3 one-time programmable (otp) registers the device contains 17 otp registers that can be used to implement system security measures and/or device identification. each otp register can be individually locked. the first 128-bit otp register is comprised of two 64-bit (8-word) segments. the lower 64-bit segment is pre-programmed at the numonyx factory with a unique 64-bit number. the upper 64-bit segment, as well as the other sixteen 128-bit otp registers, are blank. users can program these registers as needed. once programmed, users can then lock the otp register(s) to prev ent additional bit programming (see figure 14, ?otp register map? on page 41 ). each otp register has an associated lock register bit. when a lock register bit is programmed, the associated otp register can only be read; it can no longer be programmed. each otp register can be accessed multiple times to program individual 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5?15-16 1-2-3-4-5-6-7-? 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6?16-17 2-3-4-5-6-7-8-? 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7?17-18 3-4-5-6-7-8-9-? 41 4-5-6-7-8-9-10-11 4-5-6-7-8?18-19 4-5-6-7-8-9-10? 51 5-6-7-8-9-10-11-12 5-6-7-8-9?19-20 5-6-7-8-9-10-11? 61 6-7-8-9-10-11-12-13 6-7-8-9-10?20-21 6-7-8-9-10-11-12-? 71 7-8-9-10-11-12-13-14 7-8-9-10-11?21-22 7-8-9-10-11-12-13? ? ? ? ? ? ? 14 1 14-15-16-17-18?28-29 14-15-16-17-18-19-20- ? 15 1 15-16-17-18-19?29-30 15-16-17-18-19-20-21- ? table 17: burst sequence word ordering (sheet 2 of 2)
datasheet apr 2010 41 order number:208033-02 p30-65nm sbc bits, as long as the register remains unlocked. additionally, because the lock register bits themselves are otp, when programmed, lock register bits cannot be erased. therefore, when a otp register is locked, it cannot be unlocked. 11.3.1 reading the otp registers the otp registers can be read from otp-ra address. to read the otp register, first issue the read device identifier command at otp-ra address to place the device in the read device identifier state (see section 6.2, ?device command bus cycles? on page 20 ). next, perform a read operation using the address offset corresponding to the register to be read. table 8, ?device identifier information? on page 22 shows the address offsets of the otp registers and lock registers. otp registers and lock registers data is read 16 bits at a time. figure 14: otp register map 0x89 lock register 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x102 0x109 0x8a 0x91 128-bit otp register 16 (user-programmable) 128-bit otp register 1 (user-programmable) 0x88 0x85 64-bit segment (user-programmable) 0x84 0x81 0x80 lock register 0 64-bit segment (factory-programmed) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 128-bit otp register 0
p30-65nm sbc datasheet apr 2010 42 order number: 208033-02 11.3.2 programming the otp registers to program an otp register, first issue the otp register program setup command at the device base address plus the offset address of the desired otp register location (otp-ra: see figure 14, ?otp register map? on page 41 ). next, write the desired otp register data to the same otp register address. see section 6.2, ?device command bus cycles? on page 20 . the device programs the 64-bit and sixteen 128-bit user-programmable otp register data 16 bits at a time (see figure 40, ?otp register programming flowchart? on page 81 ). issuing the otp register program setup command outside of the otp register?s address space causes a program error (sr.4 set). attempting to program a locked otp register causes a program error (sr.4 set) and a lock error (sr.1 set). 11.3.3 locking the otp registers each otp register can be locked by programming its respective lock bit in the lock register. to lock an otp register, program the corresponding bit in the lock register by issuing the lock register program setup command, followed by the desired lock register data (see section 6.2, ?device command bus cycles? on page 20 ). the physical addresses of the lock registers are 0x80 for register 0 and 0x89 for register 1. these addresses are used when programming the lock registers (see table 8, ?device identifier information? on page 22 ). bit 0 of lock register 0 is already programmed during the manufacturing process at numonyx factory, locking the lower half segm ent of the first 128-bit otp register. bit 1 of lock register 0 can be programmed by us er to the upper half segment of the first 128-bit otp register. when programming bit 1 of lock register 0, all other bits need to be left as ?1? such that th e data programmed is 0xfffd. lock register 1 controls the locking of the upper sixteen 128-bit otp registers. each bit of lock register 1 corresponds to a specific 128-bit otp register; e.g., programming lr1.0 locks the corresponding otp register 1. caution: after being locked, the otp registers canno t be unlocked.
datasheet apr 2010 43 order number:208033-02 p30-65nm sbc 12.0 power and reset specifications 12.1 power-up and power-down power supply sequencing is not required if vpp is connected to vcc or vccq. otherwise vcc and vccq should attain their minimum operating voltage before applying vpp. power supply transitions should only occur when rst# is low. this protects the device from accidental programming or erasure during power transitions. 12.2 reset specifications asserting rst# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. if a cpu reset occurs without a fl ash memory reset, prop er cpu initialization may not occur. this is because the flash me mory may be providing status information, instead of array data as expected. connect rst# to the same active low reset signal used for cpu initialization. also, because the device is disabled when rst# is asserted, it ignores its control inputs during power-up/down. invalid bus conditions are masked, providing a level of memory protection. table 18: power and reset num symbol parameter min max unit notes p1 t plph rst# pulse width low 100 - ns 1,2,3,4 p2 t plrh rst# low to device reset during erase - 25 s 1,3,4,7 rst# low to device reset during program - 25 1,3,4,7 p3 t vccph vcc power valid to rst# de-assertion (high) 60 - 1,4,5,6 notes: 1. these specifications are valid for all device versions (packages and speeds). 2. the device may reset if t plph is < t plph min, but this is not guaranteed. 3. not applicable if rst# is tied to vcc. 4. sampled, but not 100% tested. 5. when rst# is tied to the vcc supp ly, device will not be ready until t vccph after vcc v ccmin . 6. when rst# is tied to the vccq su pply, device will not be ready until t vccph after vcc v ccmin . 7. reset completes within t plph if rst# is asserted while no eras e or program operation is executing.
p30-65nm sbc datasheet apr 2010 44 order number: 208033-02 12.3 power supply decoupling flash memory devices require careful power supply de-coupling. three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when ce # and oe# are asserted and deasserted. when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal lo gic states change at high speed. all of these internal activities produce transient signals. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. because flash memory devices draw their po wer from vcc, vpp, and vccq, each power connection should have a 0.1 f ceramic capacitor to ground. high-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance. figure 15: reset operation waveforms ( a) reset during read mode (b) reset during program or block erase p1 p2 (c) reset during program or block erase p1 p2 v ih v il v ih v il v ih v il rst# [p] rst# [p] rst# [p] abort complete abort complete v cc 0v v cc (d) vcc power-up to rst# high p1 r5 p2 p3 p2 r5 r5
datasheet apr 2010 45 order number:208033-02 p30-65nm sbc 13.0 maximum ratings and operating conditions 13.1 absolute maximum ratings warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. 13.2 operating conditions note: operation beyond the operating conditio ns is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 19: absolute maximum ratings parameter maximum rating notes temperature under bias ?40c to +85c - storage temperature ?65c to +125c - voltage on any signal (except vcc, vpp and vccq) ?0.5v to +4.1v 1 vpp voltage ?0.2v to +10.0v 1,2,3 vcc voltage ?0.2v to +2.5v 1 vccq voltage ?0.2v to +4.1v 1 output short circuit current 100ma 4 notes: 1. voltages shown are specified with respect to v ss . minimum dc voltage is ?0.5v on input/output signals and ?0.2v on vcc, vccq, and vpp. during transitions, this level may unde rshoot to ?2.0v for periods less than 20ns. maximum dc voltage on vcc is vcc + 0.5v, which, during transitions, may overshoot to vcc + 2.0v for periods less than 20ns. maximum dc voltage on input/output signals and vccq is vccq + 0.5v, which, during transitions, may overshoot to vccq + 2.0v for periods less than 20ns. 2. maximum dc voltage on vpp may overshoot to +11.5v for periods less than 20ns. 3. program/erase voltage is typi cally 1.7v ? 2.0v. 9.0v can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9.0v program/erase volt age may reduce bloc k cycling capability. 4. output shorted for no more th an one second. no more than one output shorted at a time. table 20: operating conditions symbol parameter min max unit notes t c operating temperature ?40 +85 c 1 vcc vcc supply voltage 1.7 2.0 v - vccq i/o supply voltage cmos inputs 1.7 3.6 ttl inputs 2.4 3.6 v ppl v pp voltage supply (l ogic level) 0.9 3.6 2 v pph buffered enhanced factory programming v pp 8.5 9.5 t pph maximum v pp hours vpp = v pph - 80 hours block erase cycles main and parameter blocks vpp = v ppl 100,000 - cycles main blocks vpp = v pph - 1000 parameter blocks vpp = v pph - 2500 notes: 1. t c = case temperature. 2. in typical operation vpp program voltage is v ppl .
p30-65nm sbc datasheet apr 2010 46 order number: 208033-02 14.0 electrical specifications 14.1 dc current characteristics table 21: dc current characteristics (sheet 1 of 2) sym parameter cmos inputs (vccq = 1.7v - 3.6v) ttl inputs (vccq = 2.4v - 3.6v) unit test conditions notes typ max typ max i li input load current - 1 - 2 a vcc = v cc max vccq = vccq max v in = vccq or v ss 1,6 i lo output leakage current dq[15:0], wait - 1 - 10 a vcc = vcc max vccq = vccq max v in = vccq or v ss i ccs , i ccd vcc standby, power-down 128-mbit 30 55 710 2000 a vcc = vcc max vccq = vcc max ce# =vccq rst# = vccq (for i ccs ) rst# = v ss (for i ccd ) wp# = v ih 1,2 64-mbit 30 55 710 2000 i ccr average vcc read current asynchronous single- word f = 5mhz (1 clk) 20 25 - - ma 8-word read vcc = vccmax ce# = v il oe# = v ih inputs: v il or v ih 1 page-mode read f = 13mhz (17 clk) 12 16 - - ma 8-word read synchronous burst f = 52mhz, lc=4 16 19 - - ma 4-word read 19 22 - - ma 8-word read 22 26 - - ma 16-word read 23 28 - - ma continuous read i ccw, i cce vcc program current, vcc erase current 35 50 35 50 ma vpp = v ppl , pgm/ers in progress 1,3,5 26 33 26 33 vpp = v pph , pgm/ers in progress 1,3,5 i ccws, i cces vcc program suspend current, vcc erase suspend current 128-mbit 30 55 710 2000 a ce# = vccq; suspend in progress 1,3,4 64-mbit 30 55 710 2000 i pps, i ppws, ippes vpp standby current, vpp program suspend current, vpp erase suspend current 0.2 5 0.2 5 a vpp = v ppl , suspend in progress 1,3,7 i ppr vpp read 2 15 2 15 a vpp = v ppl 1,3 i ppw vpp program current 0.05 0.10 0.05 0.10 ma vpp = v ppl, program in progress 3 5 10 5 10 vpp = v pph, program in progress i ppe v pp erase current 0.05 0.10 0.05 0.10 ma vpp = v ppl, erase in progress 3 5 10 5 10 vpp = v pph, erase in progress
datasheet apr 2010 47 order number:208033-02 p30-65nm sbc 14.2 dc voltage characteristics i ppbc vpp blank check 0.05 0.10 0.05 0.10 ma vpp = v ppl, erase in progress 3 5 10 5 10 vpp = v pph, erase in progress notes: 1. all currents are rms unless noted. typical values at typical vcc, t c = +25c. 2. i ccs is the average current measured over any 5ms time interval 5s after ce# is deasserted. 3. sampled, not 100% tested. 4. i cces is specified with the device de selected. if device is read while in erase suspend, current is i cces plus i ccr . 5. i ccw , i cce measured over typical or max times specified in section 15.5, ?program and erase characteristics? on page 58 . 6. if v in > vcc the input load current increases to 10a max. 7. the i pps, i ppws, i ppes will increase to 200a when vpp/wp# is at v pph . table 22: dc voltage characteristics sym parameter cmos inputs (vccq = 1.7v ? 3.6v) ttl inputs (1) (vccq = 2.4v ? 3.6v) unit test conditions notes min max min max v il input low voltage -0.5 0.4 -0.5 0.6 v - 2 v ih input high voltage vccq ? 0.4 vccq + 0.5 2.0 vccq + 0.5 v - v ol output low voltage - 0.2 - 0.2 v vcc = vcc min vccq = vccq min i ol = 100a - v oh output high voltage vccq ? 0.2 - vccq ? 0.2 - v vcc = vcc min vccq = vccq min i oh = ?100a - v pplk vpp lock-out voltage - 0.4 - 0.4 v - 3 v lko vcc lock voltage 1.0 - 1.0 - v - - v lkoq vccq lock voltage 0.9 - 0.9 - v - - notes: 1. synchronous read mode is not supported with ttl inputs. 2. v il can undershoot to ?0.4v and v ih can overshoot to vccq + 0.4v for durations of 20ns or less. 3. vpp v pplk inhibits erase and program operations. do not use v ppl and v pph outside their valid ranges . table 21: dc current charac teristics (she et 2 of 2) sym parameter cmos inputs (vccq = 1.7v - 3.6v) ttl inputs (vccq = 2.4v - 3.6v) unit test conditions notes typ max typ max
p30-65nm sbc datasheet apr 2010 48 order number: 208033-02 15.0 ac characteristics 15.1 ac test conditions note: ac test inputs are driven at vccq for logic "1" and 0 v for logic "0." input/output timing begins/ends at vccq/2. input rise and fall times (10% to 90%) < 5ns. worst case speed occurs at v cc = vccmin. notes: 1. see the following table for component values. 2. test configuration component value for worst case speed conditions. 3. c l includes jig capacitance . figure 16: ac input/output reference waveform figure 17: transient equivalent testing load circuit table 23: test configuration component value for worst case speed conditions test configuration c l (pf) vccq min standard test 30 io_ref.wmf input v ccq /2 v ccq /2 output v ccq 0v test points device under test out c l
datasheet apr 2010 49 order number:208033-02 p30-65nm sbc 15.2 capacitance figure 18: clock input ac waveform table 24: capacitance symbol parameter signals min typ max unit condition notes c in input capacitance address, ce#, we#, oe#, rst#, clk, adv#, wp# 37 8 pf typ temp = 25c, max temp = 85c, vcc = (0v - 2.0v), vccq = (0v - 3.6v) 1 c out output capacitance data, wait 3 5 6 pf notes: 1. sampled, not 100% tested. clk [c] v ih v il r203 r202 r201 clkinput.wmf
p30-65nm sbc datasheet apr 2010 50 order number: 208033-02 15.3 ac read specifications table 25: ac read specific ations (sheet 1 of 2) num symbol parameter min max unit notes asynchronous specifications r1 t avav read cycle time easy bga/quad+ 65 - ns - tsop 75 - ns - r2 t avqv address to output valid easy bga/quad+ - 65 ns - tsop - 75 ns - r3 t elqv ce# low to output valid easy bga/quad+ - 65 ns - tsop - 75 ns - r4 t glqv oe# low to output valid - 25 ns 1,2 r5 t phqv rst# high to output valid - 150 ns 1 r6 t elqx ce# low to output in low-z 0 - ns 1,3 r7 t glqx oe# low to output in low-z 0 - ns 1,2,3 r8 t ehqz ce# high to output in high-z - 20 ns 1,3 r9 t ghqz oe# high to output in high-z - 15 ns r10 t oh output hold from first occurri ng address, ce#, or oe# change 0-ns r11 t ehel ce# pulse width high 17 - ns 1 r12 t eltv ce# low to wait valid - 17 ns r13 t ehtz ce# high to wait high-z - 20 ns 1,3 r15 t gltv oe# low to wait valid - 17 ns 1 r16 t gltx oe# low to wait in low-z 0 - ns 1,3 r17 t ghtz oe# high to wait in high-z - 20 ns latching specifications r101 t avvh address setup to adv# high 10 - ns 1 r102 t elvh ce# low to adv# high 10 - ns r103 t vlqv adv# low to output valid easy bga/quad+ - 65 ns tsop - 75 ns r104 t vlvh adv# pulse width low 10 - ns r105 t vhvl adv# pulse width high 10 - ns r106 t vhax address hold from adv# high 9 - ns 1,4 r108 t apa page address access - 25 ns 1 r111 t phvh rst# high to adv# high 30 - ns clock specifications r200 f clk clk frequency easy bga/quad+ - 52 mhz 1,3,5,6 tsop - 40 mhz r201 t clk clk period easy bga/quad+ 19.2 - ns tsop 25 - ns r202 t ch/cl clk high/low time easy bga/quad+ 5 - ns tsop 9 - ns r203 t fclk/rclk clk fall/rise time 0.3 3 ns
datasheet apr 2010 51 order number:208033-02 p30-65nm sbc note: wait shown deasserted during asynchronous read mode (rcr.10=0, wait asserted low). synchronous specifications (5) r301 t avch/l address setup to clk 9 - ns 1,6 r302 t vlch/l adv# low setup to clk 9 - ns r303 t elch/l ce# low setup to clk 9 - ns r304 t chqv / t clqv clk to output valid easy bga/quad+ - 17 ns tsop - 20 ns r305 t chqx output hold from clk easy bga/quad+ 3 - ns 1,6 tsop 5 - ns 1,6 r306 t chax address hold from clk 10 - ns 1,4,6 r307 t chtv clk to wait valid easy bga/quad+ - 17 ns 1,6 tsop - 20 ns 1,6 r311 t chvl clk valid to adv# setup 3 - ns 1 r312 t chtx wait hold from clk easy bga/quad+ 3 - ns 1,6 tsop 5 - ns 1,6 notes: 1. see figure 16, ?ac input/output reference waveform? on page 48 for timing measurements and max allowable input slew rate. 2. oe# may be delayed by up to t elqv ? t glqv after ce#?s falling edge without impact to t elqv. 3. sampled, not 100% tested. 4. address hold in synchronous burst read mode is t chax or t vhax , whichever timing specification is satisfied first. 5. synchronous burst read mode is not supported with ttl level inputs. 6. applies only to subsequent synchronous reads. figure 19: asynchronous si ngle-word read (adv# low) table 25: ac read specific ations (sheet 2 of 2) num symbol parameter min max unit notes r5 r7 r6 r17 r15 r9 r4 r8 r3 r1 r2 r1 address [a] adv#[v] ce# [e] oe# [g] wait [t] data [d/q] rst# [p]
p30-65nm sbc datasheet apr 2010 52 order number: 208033-02 note: wait shown deasserted during asynchronous read mode (rcr.10=0, wait asserted low). note: wait shown deasserted during asynchronous read mode (rcr.10=0, wait asserted low). figure 20: asynchronous sing le-word read (adv# latch) 105 r1 0 r7 r6 r17 r15 r9 r4 r8 r3 r106 r101 r r2 r1 address [a] a[3:1][a] adv#[v] ce# [e] oe# [g] wait [t] data [d/q] 104 r figure 21: asynchronous page-mode read timing valid address 0 1 2 f q1 q2 q3 q8 r108 r108 r108 r13 r6 r9 r4 r8 r3 r106 r101 r105 r105 r10 r10 r10 r10 r2 a[ ma x:4 ] [ a] a[3:1] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
datasheet apr 2010 53 order number:208033-02 p30-65nm sbc . notes: 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. this diagram illustrates the case in which an n-word burst is initiated to the flas h memory array and it is terminated by ce# deassertion after the first word in the burst. notes: 1. wait is driven per oe# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. at the end of word line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. see section 11.2.3, ?end of word line (eowl) considerations? on page 37 for more information. figure 22: synchronous single-wor d array or non-array read timing figure 23: continuous burst read, showing an output delay timing latency count r312 r305 r304 r4 r17 r307 r15 r9 r7 r8 r303 r102 r3 r104 r106 r101 r104 r105 r105 r2 r306 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q] r305 r305 r305 r305 r304 r4 r7 r312 r307 r15 r303 r102 r3 r106 r105 r105 r101 r2 r304 r304 r304 r306 r302 r301 clk [c] a ddress [a] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
p30-65nm sbc datasheet apr 2010 54 order number: 208033-02 note: wait is driven per oe# assertion during synchronous array or non-array read. wait asserted during initial latency and deasserted during valid data (rcr.10=0, wait asserted low). 15.4 ac write specifications figure 24: synchronous burst- mode four-word read timing table 26: ac write specifications (sheet 1 of 2) num symbol parameter min max unit notes w1 t phwl rst# high recovery to we# low 150 - ns 1,2,3 w2 t elwl ce# setup to we# low 0 - ns 1,2,3 w3 t wlwh we# write pulse width low 50 - ns 1,2,4 w4 t dvwh data setup to we# high 50 - ns 1,2,12 w5 t avwh address setup to we# high 50 - ns 1,2 w6 t wheh ce# hold from we# high 0 - ns w7 t whdx data hold from we# high 0 - ns w8 t whax address hold from we# high 0 - ns w9 t whwl we# pulse width high 20 - ns 1,2,5 w10 t vpwh vpp setup to we# high 200 - ns 1,2,3,7 w11 t qvvl vpp hold from status read 0 - ns w12 t qvbl wp# hold from status read 0 - ns 1,2,3,7 w13 t bhwh wp# setup to we# high 200 - ns w14 t whgl we# high to oe# low 0 - ns 1,2,9 w16 t whqv we# high to read valid t avqv + 35 - ns 1,2,3,6,10 write to asynchronous read specifications w18 t whav we# high to address valid 0 - ns 1,2,3,6,8 y a q0 q1 q2 q3 r307 r10 r304 r305 r304 r4 r7 r17 r15 r9 r8 r303 r3 r106 r102 r105 r105 r101 r2 r306 r302 r301 clk [c] a d d re ss [ a ] adv# [v] ce# [e] oe# [g] wait [t] data [d/q]
datasheet apr 2010 55 order number:208033-02 p30-65nm sbc write to synchronous read specifications w19 t whch/l we# high to clock valid 19 - ns 1,2,3,6,10 w20 t whvh we# high to adv# high 19 - ns write specifications with clock active w21 t vhwl adv# high to we# low - 27 ns 1,2,3,11 w22 t chwl clock high to we# low - 27 ns notes: 1. write timing characteristics during erase suspend are the same as write-only operations. 2. a write operation can be termin ated with either ce# or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wlwh or t eleh ) is defined from ce# or we# low (which ever occurs last) to ce# or we# high (whichever occurs first). hence, t wlwh = t eleh = t wleh = t elwh . 5. write pulse width high (t whwl or t ehel ) is defined from ce# or we# high (which ever occurs first) to ce# or we# low (whichever occurs last). hence, t whwl = t ehel = t whel = t ehwl ). 6. t whvh or t whch/l must be met when transiting from a write cycle to a synchronous burst read. 7. vpp and wp# should be at a valid level until erase or program success is determined. 8. this specification is only applicable when transiting from a write cycle to an asynchronous read. see spec w19 and w20 for synchronous read. 9. when doing a read status operation following any co mmand that alters the status register, w14 is 20ns. 10. add 10ns if the write operations result s in a rcr or block lock status change, for the subsequent read operation to reflect this change. 11. these specs are required only when the device is in a synchronous mode and clock is active during address setup phase. 12. this specification must be co mplied with by customer?s writing timing. the re sult would be unpredictable if any violation to this timing specification. figure 25: write-to-write timing table 26: ac write specifications (sheet 2 of 2) num symbol parameter min max unit notes w1 w7 w4 w7 w4 w3 w9 w3 w9 w3 w3 w6 w2 w6 w2 w8 w8 w5 w5 address [a] ce# [e] we# [w] oe# [g] data [d/q] rst# [p]
p30-65nm sbc datasheet apr 2010 56 order number: 208033-02 note: wait deasserted during asynchronous read and during write. wait high-z during write per oe# deasserted. figure 26: asynchronou s read-to-write timing figure 27: write-to-asynchronous read timing q d r5 w7 w4 r10 r7 r6 r17 r15 w6 w3 w3 w2 r9 r4 r8 r3 w8 w5 r1 r2 r1 address [a] ce# [e] oe# [g] we# [w] wait [t] data [d/q] rst# [p] d q w1 r9 r8 r4 r3 r2 w7 w4 r17 r15 w14 w18 w3 w3 r10 w6 w2 r1 r1 w8 w5 address [a] adv# [v] ce# [e] we# [w] oe# [g] wait [t] data [d/q] rst# [p]
datasheet apr 2010 57 order number:208033-02 p30-65nm sbc note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr.10=0, wait asserted low). clock is ignored during write operation. note: wait shown deasserted and high-z per oe# deassertion during write operation (rcr.10=0, wait asserted low). figure 28: synchronous read-to-write timing figure 29: write-to-synchronous read timing latency count q d d w7 r305 r304 r7 r312 r307 r16 w15 w22 w21 w9 w8 w9 w3 w22 w21 w3 w2 r8 r4 w6 r11 r13 r11 r303 r3 r104 r104 r106 r102 r105 r105 w18 w5 r101 r2 r306 r302 r301 clk [c ] address [a] adv# [v] ce# [e] oe# [g] we#[w] wait [t] data [ d/q] latency count d q q w1 r304 r305 r304 r3 w7 w4 r307 r15 r4 w20 w19 w18 w3 w3 r11 r303 r11 w6 w2 r104 r106 r104 r306 w8 w5 r302 r301 r2 clk[c ] address [a] adv#[v] ce# [ e] we# [w ] oe# [g] wait [t ] data [d /q] rst# [p]
p30-65nm sbc datasheet apr 2010 58 order number: 208033-02 15.5 program and erase characteristics table 27: program and erase specifications num symbol parameter v ppl v pph unit notes min typ max min typ max conventional word programming w200 t prog/w program time single word - 40 175 - 40 175 s 1 buffered programming w250 t prog/buffer program time aligned 16-wd, bp time (32 byte) - 70 200 - 70 200 s 1 aligned 32-wd, bp time (64 byte) - 85 200 - 85 200 one full buffer (256 words) - 284 1280 - 160 800 buffered enhanced factory programming w451 t befp/b program single byte n/a n/a n/a - 0.31 - s 1,2 w452 t befp/setup befp setup n/a n/a n/a 10 - - 1 erase and suspend w501 t ers/b erase time 128-kbyte array block - 0.5 4 0.5 4 s 1 32-kbyte parameter block - 0.4 2.5 - 0.4 2.5 w600 t susp/p suspend latency program suspend - 20 25 - 20 25 s w601 t susp/e erase suspend - 20 25 - 20 25 w602 t ers/susp erase to suspend - 500 - - 500 - 1,3 blank check w702 t bc/ab blank check array block - 3.2 - - 3.2 - ms notes: 1. typical values measured at t c = +25c and nominal voltages. performance numbers are valid for all speed versions. excludes system overhead. sampled, but not 100% tested. 2. averaged over entire device. 3. w602 is the typical time between an in itial block erase or erase resume comm and and the a subsequent erase suspend command. violating the specification repeatedly during any particular block erase may cause erase failures.
datasheet apr 2010 59 order number:208033-02 p30-65nm sbc 16.0 ordering information . note: the last digit is randomly assigned to cover packing media and/or features or other specific configuration. for further information on ordering products or for product part numbers, go to: http://www.numonyx.com/en-us/memoryproducts/pages/partnumberlookup.aspx . figure 30: decoder for discrete products f 1 2 p 3 0 b 8 s 2 j 8 product line designator 28f = numonyx ? flash memory package designator js = 56- lead tsop , lead- free rc = 64- ball easy bga, leaded pc = 64- ball easy bga, lead- free device density 128 = 128-mbit 640 = 64 - mbit product family p 30 = numonyx ? axcell tm p30 flash memory v cc = 1.7? 2.0v v ccq = 1 . 7 ? 3. 6 v device details f = 65 nm lithography parameter location b = bottom parameter t = top parameter f 7 5 speed 65ns 75ns * device features* table 28: valid combinations for discrete products 64-mbit 128-mbit js28f640p30bf75* js28f128p30bf75* js28f640p30tf75* js28f128p30tf75* pc28f640p30bf65* pc28f128p30bf65* pc28f640p30tf65* pc28f128p30tf65* rc28f640p30bf65* rc28f128p30bf65* rc28f640p30tf65* rc28f128p30tf65*
p30-65nm sbc datasheet apr 2010 60 order number: 208033-02 . note: the last digit is randomly assigned to cover packing media and/or features or other specific configuration. for further information on ordering products or for product part numbers, go to: http://www.numonyx.com/en-us/memoryproducts/pages/partnumberlookup.aspx . figure 31: decoder for scsp package product designator 48f = numonyx ? flash memory only package designator rd = scsp, leaded pf = scsp, lead-free device density 0 = no die 3 = 128- mbit product family p = numonyx ? axcell ? flash memory 0 = no second flash die device details e = 65 nm lithography parameter location b = bottom parameter t = top parameter f 3 0 p 0 b q 8 f 4 p 0 e 0 z ballout descriptor q = quad+ ballout 0 = discrete ballout i/ o voltage, ce # configuration z = individual chip enable (s) v cc = 1. 7 to 2. 0 v v ccq = 1. 7 to 3. 6 v * device features* table 29: valid combinations for quad+ package products 128-mbit pf48f3000p0zbqe* pf48f3000p0ztqe* rd48f3000p0zbqe* rd48f3000p0ztqe*
datasheet apr 2010 61 order number:208033-02 p30-65nm sbc appendix a supplemental reference information a.1 common flash interface the common flash interface (cfi) is part of an overall specification for multiple command-set and control-interface descriptions. this appendix describes the database structure containing the data returned by a read operation after issuing the read cfi command (see section 6.2, ?device command bus cycles? on page 20 ). system software can parse this database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. the system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device. a.1.1 query structure output the query database allows system software to obtain information for controlling the flash device. this section describes the device?s cfi-compliant interface that allows access to query data. query data are presented on the lowest-order data outputs (dq 7-0 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two query-structure bytes, ascii ?q? and ?r,? appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. the devi ce outputs ascii ?q? in the low byte (dq 7-0 ) and 00h in the high byte (dq 15-8 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower addre ss, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word- wide devices is always ?00h,? the leadin g ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs have 00h on the upper byte in this mode. table 30: summary of query structure outp ut as a function of device and mode device hex offset hex code a scii v alue 00010: 51 "q" device addresses 00011: 52 "r" 00012: 59 "y"
p30-65nm sbc datasheet apr 2010 62 order number: 208033-02 table 31: example of query structure output of x16 devices a.1.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database . ta b l e 3 2 summarizes the structure sub-sections and address locations. table 32: query structure note: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 08000h is block 1?s beginning location when the block size is 32-kword). 3. offset 15 defines ?p? which points to the primary numonyx-specific extended query table. a.1.3 read cfi identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). offset hex code value a x -a 1 d 15 -d 0 00010h 0051 ?q? 00011h 0052 ?r? 00012h 0059 ?y? 00013h p_id lo prvendor id# 00014h p_id hi 00015h p lo prvendor tbladr 00016h p hi 00017h a_id lo altvendor id# 00018h a_id hi ... ... ... 00001-fh reserved reserved for vendor-specific information 00010h cfi query identification string command set id and vendor data offset 0001bh system interface information device timing & voltage information 00027h device geometry definition flash device layout p (3) primary numonyx-specific extended query vendor-defined additional information specific to the primary vendor algorithm
datasheet apr 2010 63 order number:208033-02 p30-65nm sbc table 33: cfi identification offset length description add. he x code value 10h 3 query-unique ascii string ?qry? 10: --51 "q" 11: --52 "r" 12: --59 "y" 13h 2 primary vendor command set and control interf ace id code. 13: --01 16-bit id code f or vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --0a 16: --01 17h 2 alternate vendor command set and control interf ace id code. 17: --00 0000h means no second vendor-specif ied algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00
p30-65nm sbc datasheet apr 2010 64 order number: 208033-02 table 34: system interface information offset length description add hex code value 1bh 1 vcc logic supply minimum program/erase voltage bits 0-3 bcd 100 mv bits 4-7 bcd volts 1b: --17 1.7v 1ch 1 vcc logic supply maximum program/erase voltage bits 0-3 bcd 100 mv bits 4-7 bcd volts 1c: --20 2.0v 1dh 1 vpp [programming] supply mi nimum program/erase voltage bits 0-3 bcd 100 mv bits 4-7 hex volts 1d: --85 8.5v 1eh 1 vpp [programming] supply ma ximum program/erase voltage bits 0-3 bcd 100 mv bits 4-7 hex volts 1e: --95 9.5v 1fh 1 ?n? such that typical single word program time-out = 2 n -sec 1f: --06 64 s 20h 1 ?n? such that typical full buffer write time-out = 2 n -sec 20: --09 512 s 21h 1 ?n? such that typical block erase time-out = 2 n m-sec 21: --09 0.5s 22h 1 ?n? such that typical full chip erase time-out = 2 n m-sec 22: --00 na 23h 1 ?n? such that maximum wo rd program time-out = 2 n times typical 23: --02 256 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --02 2048 s 25h 1 ?n? such that maximum bl ock erase time-out = 2 n times typical 25: --03 4s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na
datasheet apr 2010 65 order number:208033-02 p30-65nm sbc a.1.4 device geometry definition table 35: device geometry definition offset length description add hex code value 27h 1 ?n? such that device size = 2 n in number of bytes 27: see table below 28h 2 flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 76543210 _ _ _ _ x64 x32 x16 x8 28: --01 x16 15 14 13 12 11 10 9 8 ________29:--00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --09 512 2b: --00 2ch 1 number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 2c: see table below 2d 4 erase block region 1 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 2d: see table below 2e: 2f: 30: 31h 4 erase block region 2 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 31: see table below 32: 33: 34: 35h 4 reserved for future erase block region information 35: see table below 36: 37: 38: address 64-mbit 128-mbit address 64-mbit 128-mbit --b --t --b --t --b --t --b --t 27: --17 --17 --18 --18 30: --00 --02 --00 --02 28: --01 --01 --01 --01 31: --3e --03 --7e --03 29: --00 --00 --00 --00 32: --00 --00 --00 --00 2a --09 --09 --09 --09 33: --00 --80 --00 --80 2b --00 --00 --00 --00 34: --02 --00 --02 --00 2c: --02 --02 --02 --02 35: --00 --00 --00 --00 2d: --03 --3e --03 --7e 36: --00 --00 --00 --00 2e: --00 --00 --00 --00 37: --00 --00 --00 --00 2f: --80 -00 --80 --00 38: --00 --00 --00 --00
p30-65nm sbc datasheet apr 2010 66 order number: 208033-02 a.1.5 numonyx-specific extended query table table 36: primary vendor-specific extended query offs e t (1) length description hex p = 10ah (optional flash features and com m ands) add. code value (p+0)h 3 primary extended query table 10a --50 "p" (p+1)h unique ascii string ?pri? 10b: --52 "r" (p+2)h 10c: --49 "i" (p+3)h 1 major version number, ascii 10d: --31 "1" (p+4)h 1 minor version number, ascii 10e: --34 "4" (p+5)h 4 optional feature and command support (1=yes, 0=no) 10f: --e6 (p+6)h bits 10?31 are reserved; undefined bits are ?0.? if bit 31 is 110: --01 (p+7)h ?1? then another 31 bit field of optional features follows at 111: --00 (p+8)h the end of the bit?30 field. 112: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 0 no bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 1 yes bit 6 protection bits supported bit 6 = 1 yes bit 7 pagemode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 1 yes bit 9 simultaneous operations supported bit 9 = 0 no bit 10 extended flash array blocks supported bit 10 = 0 no bit 11 permanent block locking of up to full main array supported bit 11 = 0 no bit 12 permanent block locking of up to partial main array supported bit 12 = 0 no bit 30 cfi link(s) to follow bit 30 = 0 no bit 31 another "optional features" field to follow bit 31 = 0 no (p+9)h 1 113: --01 bit 0 program supported af ter erase suspend bit 0 = 1 yes (p+a)h 2 block status register mask 114: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 115: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-dow n bit status active bit 1 = 1 yes bit 4 efa block lock-bit status register active bit 4 = 0 no bit 5 efa block lock-dow n bit status active bit 5 = 0 no (p+c)h 1 116: --18 1.8v (p+d)h 1 117: --90 9.0v supported f unctions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undef ined bits are ?0? v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts v cc logic supply highest perf ormance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts
datasheet apr 2010 67 order number:208033-02 p30-65nm sbc table 37: otp register information offset (1) length description hex p = 10ah (optional flash features and commands) add. code value (p+e)h 1 118: --02 2 (p+f)h 4 protection field 1: protection description 119: --80 80h (p+10)h this f ield describes user-available one time programmable 11a: --00 00h (p+11)h (otp) protection register bytes. some are pre-programmed 11b: --03 8 byte (p+12)h 11c: --03 8 byte (p+13)h 10 protection field 2: protection description 11d: --89 89h (p+14)h 11e: --00 00h (p+15)h 11f: --00 00h (p+16)h 120: --00 00h (p+17)h 121: --00 0 (p+18)h bits 40?47 = ?n? such that n = f actory pgm'd groups (high byte) 122: --00 0 (p+19)h 123: --00 0 (p+1a)h 124: --10 16 (p+1b)h 125: --00 0 (p+1c)h 126: --04 16 bits 48?55 = ?n? \ 2n = f actory programmable bytes/group bits 56?63 = ?n? such that n = user pgm'd groups (low byte) bits 64?71 = ?n? such that n = user pgm'd groups (high byte) bits 72?79 = ?n? such that 2 n = user programmable bytes/group w ith device-unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s f irst byte. the f ollow ing bytes are f actory pre-programmed and user-programmable. bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec-plane physical high address bits 16?23 = ?n? such that 2n = f actory pre-programmed bytes bits 24?31 = ?n? such that 2n = user programmable bytes bits 0?31 point to the protection register physical lock-w ord address in the jedec-plane. follow ing bytes are f actory or user-programmable. bits 32?39 = ?n? such that n = f actory pgm'd groups (low byte) number of protection register f ields in jedec id space. ?00h,? indicates that 256 protection f ields are available
p30-65nm sbc datasheet apr 2010 68 order number: 208033-02 table 39: partition and erase block region information table 38: burst read information offset p=10ah length description (optional flash features and commands) add. hex code value (p+1d)h 1 page mode read capability bits 0-7 = ?n? such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 127: --04 16 byte (p+1e)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 128: --04 4 (p+1f)h 1 synchronous mode read capability configuration 1 bits 3-7 = reserved bits 0-2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 129: --01 4 (p+20)h 1 synchronous mo de read capability configuration 2 12a: --02 8 (p+21)h 1 synchronous mode read capability configuration 3 12b: --03 16 (p+22)h 1 synchronous mode read capability configuration 4 12c: --07 cont offset (1) se e table be low p = 10ah description address bottom top (optional flash features and commands) len bot top (p+23)h (p+23)h 1 12d: 12d: number of device hardw are-partition regions w ithin the device. x = 0: a single hardw are partition device (no f ields f ollow ). x specif ies the number of device partition regions containing one or more contiguous erase block regions.
datasheet apr 2010 69 order number:208033-02 p30-65nm sbc table 40: partition region 1 information (s heet 1 of 2) offset (1) se e table be low p = 10ah description address bottom top (optional flash features and commands) len bot top (p+24)h (p+24)h data size of this parition region information field 2 12e: 12e (p+25)h (p+25)h (# addressable locations, including this f ield) 12f 12f (p+26)h (p+26)h number of identical partitions w ithin the partition region 2 130: 130: (p+27)h (p+27)h 131: 131: (p+28)h (p+28)h 1 132: 132: (p+29)h (p+29)h 1 133: 133: (p+2a)h (p+2a)h 1 134: 134: (p+2b)h (p+2b)h 1 135: 135: types of erase block regions in this partition region. x = 0 = no erase blocking; the partition region erases in bulk x = number of erase block regions w / contiguous same-size erase blocks. symmetrically blocked partitions have one blocking region. partition size = (type 1 blocks)x(type 1 block sizes) + (type 2 blocks)x(type 2 block sizes) +?+ (type n blocks)x(type n block sizes) number of program or erase operations allow ed in a partition bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allow ed in other partitions w hile a partition in this region is in program mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations simultaneous program or erase operations allow ed in other partitions w hile a partition in this region is in erase mode bits 0?3 = number of simultaneous program operations bits 4?7 = number of simultaneous erase operations
p30-65nm sbc datasheet apr 2010 70 order number: 208033-02 table 41: partition region 1 information (sheet 2 of 2) offset (1) see table below p = 10ah description address bottom top (optional flash features and commands) len bot top (p+2c)h (p+2c)h partition region 1 erase block type 1 inf ormation 4 136: 136: (p+2d)h (p+2d)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 137: 137: (p+2e)h (p+2e)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 138: 138: (p+2f)h (p+2f)h 139: 139: (p+30)h (p+30)h partition 1 (erase block type 1) 2 13a: 13a: (p+31)h (p+31)h block erase cycles x 1000 13b: 13b: (p+32)h (p+32)h 1 13c: 13c: (p+33)h (p+33)h 1 13d: 13d: partition region 1 (erase block type 1) programming region information 6 (p+34)h (p+34)h bits 0?7 = x, 2^x = programming region aligned size ( bytes )13e: 13e: (p+35)h (p+35)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 13f: 13f: (p+36)h (p+36)h bits 16?23 = y = control mode valid size in bytes 140: 140: (p+37)h (p+37)h bits 24-31 = reserved 141: 141: (p+38)h (p+38)h bits 32-39 = z = control mode invalid size in bytes 142: 142: (p+39)h (p+39)h bits 40-46 = reserved; bit 47 = legacy f lash operation (ignore 23:16 & 39:32) 143: 143: (p+3a)h (p+3a)h partition region 1 erase block type 2 inf ormation 4 144: 144: (p+3b)h (p+3b)h bits 0?15 = y, y+1 = # identical-size erase blks in a partition 145: 145: (p+3c)h (p+3c)h bits 16?31 = z, region erase block(s) size are z x 256 bytes 146: 146: (p+3d)h (p+3d)h 147: 147: (p+3e)h (p+3e)h partition 1 (erase block type 2) 2 148: 148: (p+3f)h (p+3f)h block erase cycles x 1000 149: 149: (p+40)h (p+40)h 1 14a: 14a: (p+41)h (p+41)h 1 14b: 14b: partition region 1 (erase block type 2) programming region information 6 (p+42)h (p+42)h bits 0?7 = x, 2^x = programming region aligned size ( bytes )14c: 14c: (p+43)h (p+43)h bits 8?14 = reserved; bit 15 = legacy flash operation (ignore 0:7) 14d: 14d: (p+44)h (p+44)h bits 16?23 = y = control mode valid size in bytes 14e: 14e: (p+45)h (p+45)h bits 24-31 = reserved 14f: 14f: (p+46)h (p+46)h bits 32-39 = z = control mode invalid size in bytes 150: 150: (p+47)h (p+47)h bits 40-46 = reserved; bit 47 = legacy f lash operation (ignore 23:16 & 39:32) 151: 151: partition 1 (erase block type 2) bits per cell; internal edac bits 0?3 = bits per cell in erase region bit 4 = internal edac used (1=yes, 0=no) bits 5?7 = reserve f or future use partition 1 (erase block type 2) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host w rites permitte partition 1 (erase block type 1) page mode and synchronous mode capabilities defined in table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host w rites permitted (1=yes, 0=no) bits 3?7 = reserved f or future use partition 1 (erase block type 1) bits per cell; internal edac bits 0?3 = bits per cell in erase region bit 4 = internal edac used (1=yes, 0=no) bits 5?7 = reserve f or future use
datasheet apr 2010 71 order number:208033-02 p30-65nm sbc table 42: partition and erase block region information add 64-mbit 128-mbit --b --t --b --t 12d: --01 --01 --01 --01 12e: --24 --24 --24 --24 12f: --00 --00 --00 --00 130: --01 --01 --01 --01 131: --00 --00 --00 --00 132: --11 --11 --11 --11 133: --00 --00 --00 --00 134: --00 --00 --00 --00 135: --02 --02 --02 --02 136: --03 --3e --03 --7e 137: --00 --00 --00 --00 138: --80 --00 --80 --00 139: --00 --02 --00 --02 13a: --64 --64 --64 --64 13b: --00 --00 --00 --00 13c: --02 --02 --02 --02 13d: --03 --03 --03 --03 13e: --00 --00 --00 --00 13f: --80 --80 --80 --80 140: --00 --00 --00 --00 141: --00 --00 --00 --00 142 --00 --00 --00 --00 143: --80 --80 --80 --80 144: --3e --03 --7e --03 145: --00 --00 --00 --00 146: --00 --80 --00 --80 147: --02 --00 --02 --00 148: --64 --64 --64 --64 149: --00 --00 --00 --00 14a: --02 --02 --02 --02 14b: --03 --03 --03 --03 14c: --00 --00 --00 --00 14d: --80 --80 --80 --80 14e: --00 --00 --00 --00 14f: --00 --00 --00 --00 150: --00 --00 --00 --00 151: --80 --80 --80 --80
p30-65nm sbc datasheet apr 2010 72 order number: 208033-02 table 43: cfi link information length description hex (optional flash features and commands) add. code value 4 cfi link field bit def initions 152: bits 0?9 = address of f set (w ithin 32mbit segment) of ref erenced cfi table 153: bits 10?27 = nth 32mbit segment of ref erenced cfi table 154: bits 28?30 = memory type 155: bit 31 = another cfi link f ield immediately f ollow s 1 cfi link field quantity subf ield def initions 156: bits 0?3 = quantity f ield (n such that n+1 equals quantity) bit 4 = table & die relative location bit 5 = link field & table relative location bits 6?7 = reserved --ff --ff
datasheet apr 2010 73 order number:208033-02 p30-65nm sbc a.2 flowcharts figure 32: word program flowchart start data cycle - address = location to program - data = data to program yes d7 = '1' ? end no suspend ? no yes errors ? yes no error-handler user defined routine read status register - toggle ce# or oe# to update status register - see status register flowchart program suspend see suspend/ resume flowchart command cycle - issue program command - address = location to program - data = 0x40 check ready status - read status register command not required - perform read operation - read ready status on signal d7
p30-65nm sbc datasheet apr 2010 74 order number: 208033-02 figure 33: program suspend/resume flowchart read status register sr.7 = sr.2 = read array data program completed done reading program resumed read array data 0 no 0 yes 1 1 program suspend /re sume procedure write program resume data = d0 h addr = suspended block (ba) bus operation command comments write program suspend data = b0h addr = x standby check sr .7 1 = wsm ready 0 = wsm busy standby check sr .2 1 = program suspended 0 = program completed write read array data = ffh addr = block address to read (ba) read read array data from block other than the one being programmed read status register data initiate a read cycle to update status register addr = suspended block (ba) pgm _sus .wmf start write b0h any address program suspend read status write 70h write ffh any address read array write d0h any address program resume write ffh read array write read status data = 70h addr = block to suspend (ba) write 70h any address read status any address
datasheet apr 2010 75 order number:208033-02 p30-65nm sbc figure 34: erase suspend/resume flowchart erase completed read array data 0 0 no read 1 program program loop read array data 1 start read status register sr[7 ] = sr[6 ] = erase resumed read or program ? done write write idle idle write erase suspend read array or program none none program resume data = 0xb0 addr = same partition address as above data = 0xff or 0x40 addr = any address within the suspended partition check sr[7]: 1 = wsm ready 0 = wsm busy check sr[6]: 1 = erase suspended 0 = erase completed data = 0xd0 addr = any address bus operation command comments read none status register data. addr = same partition read or write none read array or program data from/to block other than the one being erased erase suspend / resume procedure if the suspended partition was placed in read array mode or a program loop : write 0xb0, any address (er ase suspend ) write 0 x70 , same partition (read status ) write 0xd0, any address (er ase r esum e ) write 0 x70 , same partition (read status ) write 0xff, erased partition (read ar r ay ) write read status data = 0x70 addr = any partition address write read status register return partition to status mode: data = 0x70 addr = same partition yes
p30-65nm sbc datasheet apr 2010 76 order number: 208033-02 figure 35: buffer program flowchart start get next target address issue write to buffer command e8h block address read status register block address (note 7) is wsm ready ? sr. 7 = 1 = yes device supports buffer writes? set timeout or loop counter timeout or count expired ? write confirm d0h block address another buffered programming? yes no no write buffer data start address x = 0 yes 0 = n o no yes use single word programming abort bufferred program? no x = n ? write buffer data address within buffer range x = x + 1 write to another block address buffered program aborted no yes yes write word count block address notes: 1. word count values on dq 0 -dq 15 are loaded into the count register. count ranges for this device are n=0000h to 00ffh. 2. the device outputs the status register when read. 3. write buffer contents will be programmed at the device start address or destination flash address . 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a 8 -a 1 of the start address =0). 5. the device aborts the buffered program command if the current address is outside the original block address . 6. the status register indicates an ?improper command sequence? if the buffered program command is aborted. follow this with a clear status register command . 7. the device defaults to output sr data after the buffered programming setup command (e8h) is issued . ce# or oe# must be be toggled to update status register . don?t issue the read sr command (70h), which would be interpreted by the internal state machine as buffer word count . 8. full status check can be done after all erase and write sequences complete . write ffh after the last operation to reset the device to read array mode. . . . bus operation standby read command write write to buffer read (note 7) standby comments check sr .7 1 = wsm ready 0 = wsm busy status register data ce# and oe# low updates sr addr = block address data = e8h addr = block address sr. 7 = valid addr = block address check sr .7 1 = device wsm is busy 0 = device wsm is ready write program confirm data = d0h addr = block address write ( notes 1, 2) data = n- 1 = word count n = 0 corresponds to count = 1 addr = block address write ( notes 3, 4) data = write buffer data addr = address within buffer range write ( notes 5, 6) data = write buffer data addr = block address suspend program loop read status register sr. 7 =? full status check if desired program complete suspend program 1 0 no yes clear status register 50h address within device yes
datasheet apr 2010 77 order number:208033-02 p30-65nm sbc figure 36: program suspend/resume flowchart read status register sr.7 = sr.2 = read array data program completed done reading program resumed read array data 0 no 0 yes 1 1 program suspend /resume procedure write program resume data = d0 h addr = suspended block (ba) bus operation command comments write program suspend data = b0h addr = x standby check sr .7 1 = wsm ready 0 = wsm busy standby check sr .2 1 = program suspended 0 = program completed write read array data = ffh addr = block address to read (ba) read read array data from block other than the one being programmed read status register data initiate a read cycle to update status register addr = suspended block (ba) pgm _sus .wmf start write b0h any address program suspend read status write 70h write ffh any address read array write d0h any address program resume write ffh read array write read status data = 70h addr = block to suspend (ba) write 70h any address read status any address
p30-65nm sbc datasheet apr 2010 78 order number: 208033-02 figure 37: befp flowchart sr error handler (user-defined) befp setup delay yes (sr.7=0) a issue befp setup cmd (data = 0x80) issue befp confirm cmd (data = 00d0h) read status register no (sr.7=1) exit start yes (sr.0=0) no (sr.0=1) write 0xffffh outside block no (sr.0=1) yes (sr.0=0) no yes yes (sr.7=1) no (sr.7=0) finish no yes befp setup done ? full status register check for errors read status register buffer ready ? write data word to buffer buffer full ? read status register program done ? program more data ? program/verify phase setup phase exit phase a b b befp exited ? read status register
datasheet apr 2010 79 order number:208033-02 p30-65nm sbc figure 38: block erase flowchart start confirm cycle - issue confirm command - address = block to be erased - data = erase confirm (0xd0) errors ? yes no error-handler user defined routine check ready status - read status register command not required - perform read operation - read ready status on signal sr.7 command cycle - issue erase command - address = block to be erased - data = 0x20 yes sr.7 = '1' ? end no suspend ? no yes read status register - toggle ce# or oe# to update status register - see status register flowchart erase suspend see suspend/ resume flowchart
p30-65nm sbc datasheet apr 2010 80 order number: 208033-02 figure 39: block lock operations flowchart no op tion al start write 60 h block address write 90 h read block lock status locking change ? lock change complete write 01 ,d0,2fh block address write ffh any address yes write write write ( optional) read ( optional) standby ( optional) write lock setup lock, unlock, or lockdown confirm read id plane block lock status read array data = 60h addr = block to lock/unlock/lock-down (ba) data = 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr = block to lock/unlock/lock-down (ba) data = 90h addr = block address offset +2 ( ba+2 ) block lock status data addr = block address offset +2 ( ba+2 ) confirm locking change on dq 1 , dq 0 . (see block locking state transitions table for valid combinations.) data = ffh addr = block address (ba) bus operation command comments locking operations procedure lock_op.wmf lock confirm lock setup read id plane read ar ray
datasheet apr 2010 81 order number:208033-02 p30-65nm sbc figure 40: otp register programming flowchart start confirm data - write otp address and data yes sr.7 = '1' ? end no read status register - toggle ce# or oe# to update status register - see status register flowchart otp program setup - write 0xc0 - otp address check ready status - read status register command not required - perform read operation - read ready status on signal sr.7
p30-65nm sbc datasheet apr 2010 82 order number: 208033-02 figure 41: status register flowchart start sr7 = '1' sr2 = '1' sr4 = '1' sr3 = '1' sr1 = '1' yes yes no yes no no no sr6 = '1' yes no sr5 = '1' no no program suspend see suspend /resume flowchart erase suspend see suspend /resume flowchart error command sequence yes yes yes error erase failure error program failure error v pen/pp < v penlk/pplk error block locked -set by wsm - reset by user - see clear status register command - set/reset by wsm sr4 = '1' yes no end command cycle - issue status register command - address = any device address - data = 0x70 data cycle - read status register sr[7:0]
datasheet apr 2010 83 order number:208033-02 p30-65nm sbc a.3 write state machine show here are the command state transitions (next state table) based on incoming commands. only one partition can be actively programming or erasing at a time. each partition stays in its last read state (read array, read device id, read cfi or read status register) until a new command change s it. the next wsm state does not depend on the partition?s output state. note: is refers to illegal state in the next state tables. table 44: next state table for p3x-65nm (sheet 1 of 3) command input and resulting chip next state (1) current chip state array read (3) word pgm setup (4,9) bp setup (8) efi command setup erase setup (4,9) befp setup (6) confirm (7) pgm/ers suspend read status clear sr (5) read id/query lock/rcr/ecr setup blank check otp setup lock blk confirm (7) lock-down blk confirm (7) write ecr/rcr confirm (7) block address change other commands (2) wsm operation completes (ffh) (40h) (e8h) (ebh) (20h) (80h) (d0h) (b0) (70h) (50h) (90h, 98h) (60h) (bch) (c0h) (01h) (2fh) (03h, 04h) other ready ready program setup bp setup efi setup erase setup befp setup ready lock/rcr /ecr setup bc setup otp setup ready n/a ready n/a lock/rcr/ecr setup ready (lock error [botch]) ready (unlock block) ready (lock error [botch]) ready (lock error [botc h]) ready (lock block ) ready (lock down block ) ready (set cr) n/a ready (lock error [botch]) n/a otp setup otp busy otp busy n/a otp busy n/a busy otp busy is in otp busy otp busy is in otp busy otp busy illegal state in otp busy otp busy n/a otp busy ready is in otp busy otp busy otp busy word program setup word program busy n/a pgm busy n/a busy pgm busy is in pgm busy pgm busy is in pgm busy pgm busy pgm susp word pgm busy is in word pgm busy word pgm busy n/a pgm busy ready is in pgm busy word pgm busy suspend pgm susp is in pgm susp pgm suspend is in pgm susp pgm busy pgm susp pgm susp (er bits clear) word pgm susp illegal state in pgm suspend word program suspend n/a word pgm susp n/a is in pgm suspend word program suspend efi efi setup sub-function setup n/a sub-function setup sub-op-code load 1 sub-op-code load 1 sub-function load 2 if word count >0, else sub-function confirm sub-function load 2 sub-function confirm if data load in program buffer is complete, else sub-function load 2 sub-function confirm ready (error [botch]) s-fn busy ready (error [botch]) sub-function busy s-fn busy is in s-fn busy s-fn busy illegal state in s-fn busy s-fn busy s-fn susp s-fn busy is in s-fn busy s-fn busy s-fn busy ready is in sub- function busy sub-function busy sub-function susp s-fn susp is in s-fn susp sub-function illegal state in s-fn busy s-fn busy s-fn suspend s-fn susp (er bits clear) s-fn susp is in s-fn susp s-fn suspend n/a s-fn susp n/a is in s-fn susp sub-function suspend
p30-65nm sbc datasheet apr 2010 84 order number: 208033-02 buffer pgm (bp) setup bp load 1 n/a bp load 1 (8) bp load 2 if word count >0, else bp confirm bp load 2 (8) bp confirm if data load in program buffer is complete, else bp load 2 ready (error [botc h]) bp confirm if data load in program buffer is complete, else bp load 2 bp confirm ready (error [botch]) bp busy ready (error [botch]) bp busy bp busy is in bp busy bp busy illegal state in bp busy bp busy bp susp bp busy is in bp busy bp busy bp busy ready is in bp busy bp busy bp susp bp susp is in bp susp bp suspend illegal state in bp busy bp busy bp suspend bp susp (er bits clear) bp susp is in bp susp bp suspend n/a bp susp n/a is in bp susp bp suspend erase setup ready (error [botch]) erase busy ready (error [botch]) n/a ready (err botch0]) n/a busy erase busy is in erase busy erase busy is in erase busy erase busy erase susp erase busy is in erase bu sy erase busy n/a ers busy is in erase busy erase busy ready suspend erase susp word pgm setup in erase susp bp setup in erase susp efi setup in erase susp is in erase suspend erase busy erase suspend erase susp (er bits clear) erase susp lock/ rcr/ ecr setup in erase susp erase susp is in erase susp erase suspend n/a erase susp n/a is in erase susp erase suspend word pgm in erase suspend setup word pgm busy in erase suspend n/a word pgm busy in ers suspend n/a busy word pgm busy in erase susp is in pgm busy in ers susp word pgm busy in erase susp is in word pgm busy in ers susp word pgm busy in erase susp word pgm susp in ers susp word pgm busy in erase susp is in word pgm busy in ers susp word pgm busy in erase susp erase susp illegal state(is) in pgm busy in erase suspend word pgm busy in erase suspend is in ers susp suspend word pgm susp in ers susp is in pgm susp in ers susp word pgm susp in ers susp is in pgm susp in ers susp word pgm busy in erase susp word pgm susp in ers susp word pgm susp in ers susp word pgm susp in ers susp (er bits clear) word pgm susp in ers susp is in word pgm susp in ers susp word pgm susp in ers susp n/a n/a illegal state in word program suspend in erase suspend word pgm busy in erase suspend bp in erase suspend setup bp load 1 in erase suspend n/a bp load 1 (8) bp load 2 in erase suspend if word count >0, else bp confirm bp load 2 (8) bp confirming erase suspend if data load in program buffer is complete, else bp load 2 in erase suspend ers susp (error [botc h]) bp confirm in erase suspend when count=0, else bp load 2 bp confirm erase suspend (error [botchbp]) bp busy in ers susp erase susp (error [botch bp]) bp busy bp busy in ers susp is in bp busy in ers susp bp busy in erase susp illegal state in bp busy in ers susp bp susp in ers susp bp busy in ers susp is in bp busy in erase suspend bp busy in ers susp n/a bp busy in ers susp erase susp is in bp busy bp busy in erase suspend is in ers susp bp susp bp susp in ers susp is in bp susp in ers susp bp suspend in erase suspend illegal state in bp busy in ers susp bp busy in ers susp bp susp in ers susp bp susp in ers susp (er bits clear) bp susp in ers susp is in bp busy in erase suspend bp susp in ers susp n/a bp susp in ers susp n/a is in bp suspend bp suspend in erase suspend table 44: next state table for p3x-65nm (sheet 2 of 3) command input and resulting chip next state (1) current chip state array read (3) word pgm setup (4,9) bp setup (8) efi command setup erase setup (4,9) befp setup (6) confirm (7) pgm/ers suspend read status clear sr (5) read id/query lock/rcr/ecr setup blank check otp setup lock blk confirm (7) lock-down blk confirm (7) write ecr/rcr confirm (7) block address change other commands (2) wsm operation completes (ffh) (40h) (e8h) (ebh) (20h) (80h) (d0h) (b0) (70h) (50h) (90h, 98h) (60h) (bch) (c0h) (01h) (2fh) (03h, 04h) other
datasheet apr 2010 85 order number:208033-02 p30-65nm sbc efi in erase suspend efi setup sub-function setup in erase suspend n/a sub-function setup sub-op-code load 1 in erase suspend sub-op-code load 1 sub-function load 2 in erase suspend if word count >0, else sub-function confirm in erase suspend sub-function load 2 sub-function confirm in erase suspend if data load in program buffer is complete, else sub-function load 2 ers susp (error [botc h]) sub-function confirm if data load in program buffer is complete, else sub-function load 2 sub-function confirm erase suspend (error [botch]) s-fn busy in ers susp erase suspend (error [botch]) sub-function busy s-fn busy in ers susp is in s-fn busy in ers susp s-fn busy in ers suspend illegal state in s-fn busy in ers susp s-fn susp in ers susp s-fn busy in ers susp is in s-fn busy in ers susp s-fn busy in ers susp n/a s-fn busy in ers susp erase susp is in sub- function busy sub-function busy in ers susp is in ers susp sub-function susp s-fn susp in ers susp is in s-fn susp in ers susp s-fn suspend in ers susp illegal state in s-fn busy in ers susp s-fn busy in ers susp s-fn suspend in ers susp s-fn susp in ers susp (er bits clear) s-fn susp in ers susp is in s-fn susp in ers susp s-fn suspend in ers susp n/a s-fn susp in ers susp n/a is in phase-1 susp sub-function suspend in erase suspend lock/rcr/ecr/lock efa block setup in erase suspend erase suspend (lock error [botch]) ers susp (un- lock block ) ers susp (lock error [botch]) ers susp (error [botc h]) ers susp blk lock ers susp blk lk- down ers susp cr set n/a ers susp (error [botch]) n/a blank check setup ready (error [botch]) bc busy ready (error [botch]) n/a ready (error [botch]) n/a blank check busy bc busy is in bc busy bc busy is in bc busy blank check busy is in bc busy bc busy bc busy ready is in blank check busy bp busy befp setup ready (error [botch]) befp load data ready (error [botch]) n/a befp busy befp program and verify busy (if block address given matches address given on befp setup command). commands treated as data. (7) ready befp busy ready table 44: next state table for p3x-65nm (sheet 3 of 3) command input and resulting chip next state (1) current chip state array read (3) word pgm setup (4,9) bp setup (8) efi command setup erase setup (4,9) befp setup (6) confirm (7) pgm/ers suspend read status clear sr (5) read id/query lock/rcr/ecr setup blank check otp setup lock blk confirm (7) lock-down blk confirm (7) write ecr/rcr confirm (7) block address change other commands (2) wsm operation completes (ffh) (40h) (e8h) (ebh) (20h) (80h) (d0h) (b0) (70h) (50h) (90h, 98h) (60h) (bch) (c0h) (01h) (2fh) (03h, 04h) other
p30-65nm sbc datasheet apr 2010 86 order number: 208033-02 notes: 1. is refers to illegal state in the next state table. 2. ?illegal commands? include commands outside of the allowed command set. 3. the device defaults to "read array" on powerup. 4. if a ?read array? is attempted when the device is busy, the re sult will be ?garbage? data (w e should not tell the user that it will actually be status register data). the key point is th at the output mux will be pointing to the ?array?, but garbage data will be output. ?read id? and "read query" commands do the exact same thing in the device. th e id and query data are located at different lo cations in the address map. 5. the clear status command only clears the error bits in the stat us register if the device is not in the following modes:1. wsm running (pgm busy, erase busy, pgm busy in erase suspend, otp busy, befp modes) 2. suspend states (erase suspend, pgm suspend, pgm suspend in erase suspend). 6. befp writes are only allowed when the status re gister bit #0 = 0 or else the data is ignored. 7. confirm commands (lock block, unlock block, lock-down bl ock, configuration register and blank check) perform the operation and then move to the ready state. 8. buffered programming will botch when a different block address (as compared to the address given on the first data write cycle) is written during the bp load1 and bp load2 states. 9. all two cycle commands will be considered as a contiguous w hole during device suspend states. individual commands will not be parsed separately. (i.e. if an erase set-up command is issued followed by a d0h command, the d0h command will not resume the program op eration. issuing the erase set-up places the cui in an ?illega l state?. a subsequent command will clear the ?illegal state?, but th e command will be otherwise ignored. table 45: output next state table for p3x-65nm command input to chip and resulting output mux next state (1) current chip state array read (3) word pgm setup (4,9) bp setup (8) efi command setup erase setup (4,9) befp setup (6) confirm (7) pgm/ers suspend read status clear sr (5) read id/query lock/rcr/ecr setup blank check otp setup lock blk confirm (7) lock-down blk confirm (7) write ecr/rcr confirm (7) block address change other commands (2) wsm operation completes (ffh) (40h) (e8h) (ebh) (20h) (80h) (d0h) (b0) (70h) (50h) (90h, 98h) (60h) (bch) (c0h) (01h) (2fh) (03h, 04h) other befp setup, befp pgm & verify busy, erase setup, otp setup, bp setup, load 1, load 2 bp setup, load1, load 2 - in erase susp. bp confirm efi sub-function confirm word pgm setup, word pgm setup in erase susp, bp confirm in erase suspend, efi s-fn confirm in ers susp, blank check setup, blank check busy status read output mux does not change lock/rcr/ecr setup, lock/rcr/ecr setup in erase susp status read array read efi s-fn setup, ld 1, ld 2 efi s-fn setup, ld1, ld 2 - in erase susp. output mux will not change bp busy bp busy in erase suspend efi sub-function busy efi sub-fn busy in ers susp word program busy, word pgm busy in erase suspend, otp busy erase busy status read status read status read status read output mux does not change status read array read status read status read output mux does not change ready, word pgm suspend, bp suspend, phase-1 bp suspend, erase suspend, bp suspend in erase suspend phase-1 bp susp in ers susp array read output mux doesn?t change id/query read
datasheet apr 2010 87 order number:208033-02 p30-65nm sbc appendix b conventions - additional documentation b.1 acronyms b.2 definitions and terms befp : buffer enhanced factory programming cui : command user interface cfi : common flash interface efi : extended function interface sbc : single bit per cell otp : one-time programmable plr : one-time programmable lock register pr : one-time programmable register rcr : read configuration register rfu : reserved for future use sr : status register srd : status register data wsm : write state machine vcc : signal or voltage connection v cc : signal or voltage level h : hexadecimal number suffix 0b : binary number prefix 0x : exadecimal number prefix sr.4 : denotes an individual register bit. sr[3,1] : denotes a group individual register bits. sr[3:1] : denotes a group continuous register bits. a[15:0] : denotes a group of similarly named signals, such as address or data bus. a5 : denotes one element of a signal group membership, such as an individual address bit. bit : single binary unit byte : eight bits word : two bytes, or sixteen bits kbit : 1024 bits kbyte : 1024 bytes kword : 1024 words mbit : 1,048,576 bits mbyte : 1,048,576 bytes mword : 1,048,576 words k : 1,000
p30-65nm sbc datasheet apr 2010 88 order number: 208033-02 m : 1,000,000 block : a group of bits, bytes, or words within the flash memory array that erase simultaneously. array block : an array block that is usually used to store code and/or data.
datasheet apr 2010 89 order number:208033-02 p30-65nm sbc appendix c revision history date revision description jun 2009 01 initial release apr 2010 02 update the buffered program performance, suspend latency, befp performance in table 27, ?program and erase specifications? on page 58 . update the 40mhz spec for tsop package in table 25, ?ac read specifications? on page 50 . add t dvwh timing comments in table 26, ?ac write specifications? on page 54 . reflect the program performance in cfi in table 34, ?system interface information? on page 64 . update the url for part number lookup.
p30-65nm sbc datasheet apr 2010 90 order number: 208033-02

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